Inventor

Diana L. Orf

Inventor
Somerville, MA, US

Overview

21→
Patents
2011–2021
Patent span
Physics
Primary field (CPC G)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing91%
G01RMeasuring electric variables5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
PatentTitleYear
11,119,766Hardware accelerator with locally stored macros20219,792,213'Mitigating busy time in a high performance cache'20179,594,689'Designated cache data backup during system operation'20179,298,468'Monitoring processing time in a shared pipeline'20169,158,694'Mitigating busy time in a high performance cache'20159,104,583'On demand allocation of cache buffer slots'20158,930,628'Managing in-line store throughput reduction'20158,706,970'Dynamic cache queue allocation based on destination availability'20148,671,267'Monitoring processing time in a shared pipeline'20148,560,803'Dynamic cache queue allocation based on destination availability'20138,522,076'Error detection and recovery in a shared pipeline'20138,521,960'Mitigating busy time in a high performance cache'20138,495,452'Handling corrupted background data in an out of order execution environment'20138,468,536'Multiple level linked LRU priority'20138,447,930'Managing in-line store throughput reduction'20138,447,932'Recover store data merging'20138,447,905'Dynamic multi-level cache including resource access fairness scheme'20138,392,621'Managing dataflow in a temporary memory'20138,090,883'Method, system and computer program product for enhanced shared store buffer management scheme with limited resources for optimized performance'20127,987,400'Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy'20117,886,089'Method, system and computer program product for enhanced shared store buffer management scheme for differing buffer sizes with limited resources for optimized performance'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011–2021Patents assigned to IBM (21)· patent assignee history
2011–2012Based in Hyde Park, NY, US· patent location history
2011Based in Poughkeepsie, NY, US· patent location history
2012–2013Patents assigned to ORF DIANA L (6)· patent assignee history
2013–2014Patents assigned to SONNELITTER III ROBERT J (8)· patent assignee history
2013–2015Patents assigned to AMBROLADZE EKATERINA M (6)· patent assignee history
2013–2015Patents assigned to FEE MICHAEL (6)· patent assignee history
2013–2017Based in Somerville, MA, US· patent location history
2017–2021Based in Natick, MA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM212011–2021
SONNELITTER III ROBERT J82013–2014
AMBROLADZE EKATERINA M62013–2015
FEE MICHAEL62013–2015
ORF DIANA Lself62012–2013
Locations
LocationPatentsSpan
Somerville, Massachusetts, US162013–2017
Natick, Massachusetts, US22017–2021
Hyde Park, New York, US22011–2012
Poughkeepsie, New York, US12011