Inventor

Robert P. Masleid

Inventor

Monte Sereno, CA, US

Overview

1988–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 170 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique37%

G06FElectric digital data processing18%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%

H10DInorganic electric semiconductor devices7%

G11CStatic stores7%

H04LTransmission of digital information, e.g. telegraphic communication7%

G01RMeasuring electric variables4%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses4%

H01LSemiconductor devices2%

G05FSystems for regulating electric or magnetic variables1%

PatentTitleYear

10,999,401Multiple on-die communication networks2021 10,679,945Body-bias voltage routing structures2020 10,110,700Multiple on-die communication networks2018 9,984,978Body-bias voltage routing structures2018 9,773,727'Multi-layer full dense mesh'2017 9,632,883'Digital encoding of parallel busses to suppress simultaneous switching output noise'2017 9,595,968'Cross point switch'2017 9,543,243'Low-noise arrangement for very-large-scale integration differential input/output structures'2017 9,531,361'Power efficient multiplexer'2016 9,509,317'Rotational synchronizer circuit for metastablity resolution'2016 9,484,949'Variable run length encoding of a bit stream'2016 9,406,364'Codec to reduce simultaneously switching outputs'2016 9,406,601'Body-bias voltage routing structures'2016 9,218,018'Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain'2015 9,209,813'Coarse data aligner'2015 9,178,750'Post-silicon repair of on-die networks'2015 9,178,505'Cross point switch'2015 9,160,321'Power efficient multiplexer'2015 9,136,850'Phase aligner with short lock time'2015 9,100,003'Systems and methods for adjusting threshold voltage'2015 9,036,447'Decoder circuit with reduced current leakage'2015 9,013,943'Static random access memory circuit with step regulator'2015 8,994,402'Level shifter circuit optimized for metastability resolution and integrated level shifter and metastability resolution circuit'2015 8,946,905'Via structure for integrated circuits'2015 8,943,375'Combo static flop with full test'2015 8,904,254'Combo dynamic flop with scan'2014 8,898,365'Micro-link high-bandwidth chip-to-chip bus'2014 8,878,616'Inverting difference oscillator'2014 8,697,512'Systems and methods for integrated circuits comprising multiple body biasing domains'2014 8,686,778'Integrated pulse-control and enable latch circuit'2014 8,674,739'Single-inversion pulse flop'2014 8,656,214'Dual ported replicated data cache'2014 8,633,547'Structure for spanning gap in body-bias voltage routing structure'2014 8,587,344'Power efficient multiplexer'2013 8,583,850'Micro crossbar switch and on-die data network using the same'2013 8,543,346'Near-isotropic antenna for monitoring electromagnetic signals'2013 8,525,566'Glitch hardened flop repeater'2013 8,525,550'Repeater circuit with multiplexer and state element functionality'2013 8,436,668'Min-time hardended pulse flop'2013 8,420,472'Systems and methods for integrated circuits comprising multiple body biasing domains'2013 8,385,150'Delay efficient gater repeater'2013 8,341,585'Skewed placement grid for very large scale integrated circuits'2012 8,330,515'Inverting zipper repeater circuit'2012 8,319,515'Systems and methods for adjusting threshold voltage'2012 8,305,126'Flop type selection for very large scale integrated circuits'2012 8,289,088'Inverting difference oscillator'2012 8,283,960'Minimal bubble voltage regulator'2012 8,269,544'Power-supply noise suppression using a frequency-locked loop'2012 8,269,333'Combined power mesh transition and signal overpass/underpass'2012 8,266,562'Method and system for configurable contacts for implementing different bias designs of an integrated circuit device'2012 8,242,823'Delay chain initialization'2012 8,222,914'Systems and methods for adjusting threshold voltage'2012 8,214,790'Low RC global clock distribution'2012 8,208,467'Method and apparatus for modulating the width of a high-speed link'2012 8,198,931'Fine grain timing'2012 8,179,165'Precision sampling circuit'2012 8,181,073'SRAM macro test flop'2012 8,166,438'Low RC local clock distribution'2012 8,102,190'Power efficient multiplexer'2012 8,099,689'Method and system for a tiling bias design to facilitate efficient design rule checking'2012 8,067,970'Multi-write memory circuit with a data input and a clock input'2011 8,063,673'Transit state element'2011 8,035,425'Active echo on-die repeater circuit'2011 8,030,960'Converting dynamic repeaters to conventional repeaters'2011 8,018,252'Circuit with enhanced mode and normal mode'2011 8,008,957'Inverting zipper repeater circuit'2011 8,004,307'Static-dynamic-dynamic repeater circuit'2011 7,994,836'Latch with clocked devices'2011 7,977,995'Configurable pulse generator'2011 7,880,513'Repeater circuit with staged output'2011 7,872,516'Precision pulse generator'2011 7,872,492'Triple latch flip flop system and method'2011 7,859,062'Systems and methods for integrated circuits comprising multiple body biasing domains'2010 7,847,408'Integrated clock and power distribution'2010 7,816,742'Systems and methods for integrated circuits comprising multiple body biasing domains'2010 7,816,966'Economy precision pulse generator'2010 7,802,223'Method and system for configurable contacts for implementing different bias designs of an integrated circuit device'2010 7,791,393'Precision falling edge generator'2010 7,777,523'Level shifter flip-flop'2010 7,768,295'Advanced repeater utilizing signal distribution delay'2010 7,768,356'Dynamic ring oscillators'2010 7,759,740'Deep well regions for routing body-bias voltage to mosfets in surface well regions having separation wells of p-type between the segmented deep n wells'2010 7,755,193'Non-rectilinear routing in rectilinear mesh of a metallization layer of an integrated circuit'2010 7,747,896'Dual ported replicated data cache'2010 7,737,749'Elastic pipeline latch with a safe mode'2010 7,725,656'Braided set associative caching techniques'2010 7,724,027'Method and system for elastic signal pipelining'2010 7,724,025'Leakage efficient anti-glitch filter'2010 7,710,153'Cross point switch'2010 7,710,160'Stacked inverter delay chain'2010 7,689,963'Double diamond clock and power distribution'2010 7,679,949'Column select multiplexer circuit for a domino random access memory array'2010 7,667,288'Systems and methods for voltage distribution via epitaxial layers'2010 7,663,408'Scannable dynamic circuit latch'2010 7,661,086'Enhanced clock signal flexible distribution system and method'2010 7,656,212'Configurable delay chain with switching control for tail delay elements'2010 7,652,507'Circuits and methods for detecting and assisting wire transitions'2010 7,646,228'Inverting zipper repeater circuit'2010 7,642,866'Circuits, systems and methods relating to a dynamic dual domino ring oscillator'2010 7,635,992'Configurable tapered delay chain with multiple sizes of delay elements'2009 7,598,731'Systems and methods for adjusting threshold voltage'2009 7,598,573'Systems and methods for voltage distribution via multiple epitaxial layers'2009 7,595,664'Repeater circuit having different operating and reset voltage ranges, and methods thereof'2009 7,592,836'Multi-write memory circuit with multiple data inputs'2009 7,592,842'Configurable delay chain with stacked inverter delay elements'2009 7,592,839'Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability'2009 7,579,221'Conversion of an SOI design layout to a bulk design layout'2009 7,498,846'Power efficient multiplexer'2009 7,495,466'Triple latch flip flop system and method'2009 7,414,485'Circuits, systems and methods relating to dynamic ring oscillators'2008 7,394,681'Column select multiplexer circuit for a domino random access memory array'2008 7,388,260'Structure for spanning gap in body-bias voltage routing structure'2008 7,375,556'Advanced repeater utilizing signal distribution delay'2008 7,336,103'Stacked inverter delay chain'2008 7,332,931'Leakage efficient anti-glitch filter with variable delay stages'2008 7,330,054'Leakage efficient anti-glitch filter'2008 7,313,779'Method and system for tiling a bias design to facilitate efficient design rule checking'2007 7,310,008'Configurable delay chain with stacked inverter delay elements'2007 7,304,503'Repeater circuit with high performance repeater mode and normal repeater mode, wherein high performance repeater mode has fast reset capability'2007 7,295,041'Circuits and methods for detecting and assisting wire transitions'2007 7,256,634'Elastic pipeline latch with a safe mode'2007 7,217,962'Wire mesh patterns for semiconductor devices'2007 7,205,758'Systems and methods for adjusting threshold voltage'2007 7,173,455'Repeater circuit having different operating and reset voltage ranges, and methods thereof'2007 7,142,018'Circuits and methods for detecting and assisting wire transitions'2006 7,119,580'Repeater circuit with high performance repeater mode and normal repeater mode'2006 7,071,747'Inverting zipper repeater circuit'2006 7,053,680'Complement reset buffer'2006 7,051,294'Cold clock power reduction'2006 7,049,699'Low RC structures for routing body-bias voltage'2006 6,906,579'Optimal inductor management'2005 6,864,524'Hybrid bulk/silicon-on-insulator multiprocessors'2005 6,744,242'Four-state switched decoupling capacitor system for active power stabilizer'2004 6,740,914'FET circuit block with reduced self-heating'2004 6,731,140'Complement reset multiplexer latch'2004 6,701,444'Method and apparatus for process independent clock signal distribution'2004 6,668,357'Cold clock power reduction'2003 6,630,851'Low latency clock distribution'2003 6,577,176'Complement reset latch'2003 6,552,589'Method and apparatus for process independent clock signal distribution'2003 6,532,544'High gain local clock buffer for a mesh clock distribution utilizing a gain enhanced split driver clock buffer'2003 6,525,354'FET circuit block with reduced self-heating'2003 6,389,585'Method and system for building a multiprocessor data processing system'2002 6,133,759'Decoupled reset dynamic logic circuit'2000 6,111,434'Circuit having anti-charge share characteristics and method therefore'2000 6,025,738'Gain enhanced split drive buffer'2000 6,021,512'Data processing system having memory sub-array redundancy and method therefor'2000 6,014,047'Method and apparatus for phase rotation in a phase locked loop'2000 5,949,262'Method and apparatus for coupled phase locked loops'1999 5,942,940'Low voltage CMOS differential amplifier'1999 5,894,419'System and method for robust clocking schemes for logic circuits'1999 5,892,372'Creating inversions in ripple domino logic'1999 5,870,592'Clock generation apparatus and method for CMOS microprocessors using a differential saw oscillator'1999 5,828,257'Precision time interval division with digital phase delay lines'1998 5,815,687'Apparatus and method for simulating domino logic circuits using a special machine cycle to validate pre-charge'1998 5,812,418'Cache sub-array method and apparatus for use in microprocessor integrated circuits'1998 5,729,501'High Speed SRAM with or-gate sense'1998 5,675,273'Clock regulator with precision midcycle edge timing'1997 5,668,761'Fast read domino SRAM'1997 5,656,963'Clock distribution network for reducing clock skew'1997 5,646,572'Power management system for integrated circuits'1997 5,623,450'Conditional recharge for dynamic logic'1997 5,615,160'Minimal recharge overhead circuit for domino SRAM structures'1997 5,614,845'Independent clock edge regulation'1997 5,610,548'Split drive clock buffer'1997 5,442,776'Electronically tuneable computer clocking system and method of electronically tuning distribution lines of a computer clocking system'1995 5,045,913'Bit stack compatible input/output circuits'1991 5,036,215'Pass gate multiplexer receiver circuit'1991 4,988,636'Method of making bit stack compatible input/output circuits'1991 4,771,284'Logic array with programmable element output generation'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2004Patents assigned to IBM (31)· patent assignee history

1988–2000Based in Austin, TX, US· patent location history

2002–2021Based in Monte Sereno, CA, US· patent location history

2009–2015Patents assigned to MASLEID ROBERT P (44)· patent assignee history

2009–2015Patents assigned to MASLEID ROBERT PAUL (27)· patent assignee history

2010–2014Patents assigned to ORACLE AMERICA INC (25)· patent assignee history

2012–2021Patents assigned to ORACLE INT CORP (27)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MASLEID ROBERT Pself	44	2009–2015
IBM	31	1988–2004
MASLEID ROBERT PAULself	27	2009–2015
ORACLE INT CORP	27	2012–2021
ORACLE AMERICA INC	25	2010–2014

Locations

Location	Patents	Span
Monte Sereno, California, US	143	2002–2021
Austin, Texas, US	27	1988–2000