Inventor

Ravindraraj Ramaraju

Inventor

Round Rock, TX, US

Overview

2004–2021

Patent span

Physics

Primary field (CPC G)

Patents· 111 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores37%

G06FElectric digital data processing25%

H03KPulse technique16%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%

H03MCoding3%

G05FSystems for regulating electric or magnetic variables3%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications3%

G01KMeasuring temperature2%

G01RMeasuring electric variables1%

G04FTime-interval measuring1%

PatentTitleYear

11,049,553Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein2021 10,965,305Multi-phase sampling time-to-digital converter (TDC) for jitter measurement2021 10,796,749Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein2020 10,796,748Method and circuit device incorporating time-to-transition signal node sensing2020 10,629,256Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein2020 10,269,413Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein2019 10,236,053Method and circuit device incorporating time-to-transition signal node sensing2019 10,164,768Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors2018 9,772,901'Memory reliability using error-correcting code'2017 9,719,861'Temperature sensor circuit'2017 9,672,938'Memory with redundancy'2017 9,542,334'Memory management unit TAG memory with CAM evaluate signal'2017 9,530,501'Non-volatile static random access memory (NVSRAM) having a shared port'2016 9,528,883'Temperature sensor circuitry with scaled voltage signal'2016 9,477,548'Error repair location cache'2016 9,466,394'Mismatch-compensated sense amplifier for highly scaled technology'2016 9,425,829'Adaptive error correction codes (ECCs) for electronic memories'2016 9,418,741'Content addressable memory with search line test circuitry'2016 9,400,711'Content addressable memory with error detection'2016 9,396,064'Error correction with secondary memory'2016 9,389,954'Memory redundancy to replace addresses with multiple errors'2016 9,374,093'Capacitively coupled input buffer'2016 9,367,475'System and method for cache access'2016 9,367,437'Method and apparatus for reducing the number of speculative accesses to a memory array'2016 9,323,691'Multiple page size memory management unit'2016 9,323,602'Error correction with extended CAM'2016 9,323,534'Method and apparatus for detecting a collision between multiple threads of execution for accessing a memory array'2016 9,317,087'Memory column drowsy control'2016 9,318,158'Non-volatile memory using bi-directional resistive elements'2016 9,281,042'Non-volatile memory using bi-directional resistive elements and capacitive elements'2016 9,225,337'Temperature threshold circuit with hysteresis'2015 9,224,439'Memory with word line access control'2015 9,141,451'Memory having improved reliability for certain data types'2015 9,141,552'Memory using voltage to improve reliability for certain data types'2015 9,124,262'Reconfigurable flip-flop'2015 9,117,507'Multistage voltage regulator circuit'2015 9,116,799'Method for detecting bank collision at a memory and device therefor'2015 9,117,498'Memory with power savings for unnecessary reads'2015 9,081,693'Data type dependent memory scrubbing'2015 9,081,719'Selective memory scrubbing based on data type'2015 9,059,687'Flip-flop having shared feedback and method of operation'2015 9,035,629'Voltage regulator with different inverting gain stages'2015 9,021,194'Memory management unit tag memory'2015 8,943,292'System and method for memory array access with fast address decoder'2015 8,941,427'Configurable flip-flop'2015 8,917,136'Charge pump system and method of operation'2014 8,914,712'Hierarchical error correction'2014 8,908,449'Master-slave flip-flop with reduced setup time'2014 8,861,301'Clocked memory with latching predecoder circuitry'2014 8,837,205'Multi-port register file with multiplexed data'2014 8,806,294'Error detection within a memory'2014 8,791,739'Flip-flop having shared feedback and method of operation'2014 8,755,244'Write contention-free, noise-tolerant multi-port bitcell'2014 8,743,651'Clocked memory with word line activation during a first portion of the clock cycle'2014 8,710,916'Electronic circuit having shared leakage current reduction circuits'2014 8,677,205'Hierarchical error correction for large memories'2014 8,587,356'Recoverable and reconfigurable pipeline structure for state-retention power gating'2013 8,566,836'Multi-core system on chip'2013 8,566,620'Data processing having multiple low power modes and method therefor'2013 8,542,048'Double edge triggered flip flop'2013 8,537,625'Memory voltage regulator with leakage current voltage control'2013 8,533,578'Error detection in a content addressable memory (CAM) and method of operation'2013 8,514,611'Memory with low voltage mode operation'2013 8,493,121'Reconfigurable flip-flop'2013 8,487,656'Dynamic logic circuit'2013 8,489,906'Data processor having multiple low power modes'2013 8,487,657'Dynamic logic circuit'2013 8,484,523'Sequential digital circuitry with test scan'2013 8,380,779'Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand'2013 8,379,468'Word line fault detection'2013 8,365,036'Soft error correction in a memory array and method thereof'2013 8,345,469'Static random access memory (SRAM) having bit cells accessible by separate read and write paths'2013 8,339,838'In-line register file bitcell'2012 8,319,548'Integrated circuit having low power mode voltage regulator'2012 8,199,547'Error detection in a content addressable memory (CAM)'2012 8,189,408'Memory device having shifting capability and method thereof'2012 8,143,929'Flip-flop having shared feedback and method of operation'2012 8,099,580'Translation look-aside buffer with a tag memory and method therefor'2012 7,984,229'Pipelined tag and information array access with speculative retrieval of tag that corresponds to information access'2011 7,843,218'Data latch with structural hold'2010 7,825,720'Circuit for a low power mode'2010 7,669,034'System and method for memory array access with fast address decoder'2010 7,649,764'Memory with shared write bit line(s)'2010 7,630,272'Multiple port memory with prioritized world line driver and method thereof'2009 7,626,842'Photon-based memory device and method thereof'2009 7,623,404'Memory device having concurrent write and read cycles and method thereof'2009 7,548,102'Data latch with minimal setup time and launch delay'2009 7,548,103'Storage device having low power mode and methods thereof'2009 7,545,702'Memory pipelining in an integrated circuit memory device using shared word lines'2009 7,525,867'Storage circuit and method therefor'2009 7,499,342'Dynamic module output device and method thereof'2009 7,495,493'Circuitry for latching'2009 7,489,540'Bitcell with variable-conductance transfer gate and method thereof'2009 7,453,756'Method for powering an electronic device and circuit'2008 7,440,335'Contention-free hierarchical bit line in embedded memory and method thereof'2008 7,400,545'Storage circuit with efficient sleep mode and method'2008 7,365,587'Contention-free keeper circuit and a method for contention elimination'2008 7,362,134'Circuit and method for latch bypass'2008 7,349,266'Memory device with a data hold latch'2008 7,295,487'Storage circuit and method therefor'2007 7,286,423'Bit line precharge in embedded memory'2007 7,242,626'Method and apparatus for low voltage write in a static random access memory'2007 7,215,188'Integrated circuit having a low power mode and method therefor'2007 7,200,020'Storage element with clear operation and method thereof'2007 7,193,924'Dual-port static random access memory having improved cell stability and write margin'2007 7,187,205'Integrated circuit storage element having low power data retention and method therefor'2007 7,185,170'Data processing system having translation lookaside buffer valid bits with lock and method therefor'2007 7,164,293'Dynamic latch having integral logic function and method therefor'2007 7,161,827'SRAM having improved cell stability and method therefor'2007 6,928,005'Domino comparator capable for use in a memory array'2005 6,819,538'Method and apparatus for controlling current demand in an integrated circuit'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2017Patents assigned to FREESCALE SEMICONDUCTOR INC (100)· patent assignee history

2004–2008Based in Austin, TX, US· patent location history

2005–2021Based in Round Rock, TX, US· patent location history

2012–2017Patents assigned to RAMARAJU RAVINDRARAJ (56)· patent assignee history

2012–2016Patents assigned to BEARDEN DAVID R (10)· patent assignee history

2013–2016Patents assigned to RUSSELL ANDREW C (16)· patent assignee history

2013–2017Patents assigned to HOEKSTRA GEORGE P (8)· patent assignee history

2018–2019Based in San Diego, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
FREESCALE SEMICONDUCTOR INC	100	2004–2017
RAMARAJU RAVINDRARAJself	56	2012–2017
RUSSELL ANDREW C	16	2013–2016
BEARDEN DAVID R	10	2012–2016
HOEKSTRA GEORGE P	8	2013–2017

Locations

Location	Patents	Span
Round Rock, Texas, US	106	2005–2021
San Diego, California, US	3	2018–2019
Austin, Texas, US	2	2004–2008