LexDanaLexDanabeta
Inventor

Donald C. Stark

Inventor
Los Altos, CA, US

Overview

119→
Patents
1995–2020
Patent span
Physics
Primary field (CPC G)

Patents· 119 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores40%
G06FElectric digital data processing26%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
H04LTransmission of digital information, e.g. telegraphic communication7%
H03KPulse technique5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H05KPrinted circuits3%
G01RMeasuring electric variables2%
G06TImage data processing or generation, in general2%
H04NPictorial communication, e.g. television2%
PatentTitleYear
10,719,905Architecture for high performance, power efficient, programmable image processing202010,417,732Architecture for high performance, power efficient, programmable image processing201910,397,450Two dimensional shift array for image processor201910,310,999Flash memory controller with calibrated data communication20199,965,824Architecture for high performance, power efficient, programmable image processing20189,824,036'Memory systems with multiple modules supporting simultaneous access responsive to common memory commands'20179,785,589'Memory controller that calibrates a transmit timing offset'20179,769,356'Two dimensional shift array for image processor'20179,405,678'Flash memory controller with calibrated data communication'20169,270,282'Methods and systems for switching between clocks'20169,257,151'Printed-circuit board supporting memory systems with multiple data-bus configurations'20169,164,933'Memory system with calibrated data communication'20158,948,212'Memory controller with circuitry to set memory device-specific reference voltages'20158,930,594'Integrated circuit with a pinmux crossbar and virtual pins for peripheral connectivity'20158,779,953'Fast test of digital-to-analog converters'20148,769,234'Memory modules and devices supporting configurable data widths'20148,630,317'Memory system with calibrated data communication'20148,560,797'Method and apparatus for indicating mask information'20138,412,906'Memory apparatus supporting multiple width configurations'20138,313,712'Microfluidic valve with pressure gain'20128,305,839'Memory device having multiple power modes'20128,295,107'Asynchronous pipelined memory access'20128,296,540'Method and apparatus for adjusting the performance of a synchronous memory system'20128,248,884'Method of controlling a memory device having multiple power modes'20128,205,056'Memory controller for controlling write signaling'20128,170,067'Memory system with calibrated data communication'20128,112,608'Variable-width memory'20128,102,730'Single-clock, strobeless signaling system'20128,059,476'Control component for controlling a delay interval within a memory component'20118,019,958'Memory write signaling and methods thereof'20117,986,584'Memory device having multiple power modes'20117,830,735'Asynchronous, high-bandwidth memory component using calibrated timing elements'20107,793,039'Interface for a semiconductor memory device and method for controlling the interface'20107,663,966'Single-clock, strobeless signaling system'20107,626,880'Memory device having a read pipeline and a delay locked loop'20097,535,933'Calibrated data communication system and method'20097,529,141'Asynchronous, high-bandwidth memory component using calibrated timing elements'20097,496,709'Integrated circuit memory device having delayed write timing based on read response time'20097,397,725'Single-clock, strobeless signaling system'20087,362,626'Asynchronous, high-bandwidth memory component using calibrated timing elements'20087,360,050'Integrated circuit memory device having delayed write capability'20087,353,357'Apparatus and method for pipelined memory operations'20087,337,294'Method and apparatus for adjusting the performance of a synchronous memory system'20087,331,006'Multiple sweep point testing of circuit devices'20087,330,951'Apparatus and method for pipelined memory operations'20087,330,953'Memory system having delayed write timing'20087,330,952'Integrated circuit memory device having delayed write timing based on read response time'20087,320,082'Power control system for synchronous memory device'20087,308,065'Delay locked loop circuitry for clock delay adjustment'20077,287,119'Integrated circuit memory device with delayed write command processing'20077,287,109'Method of controlling a memory device having a memory core'20077,197,611'Integrated circuit memory device having write latency function'20077,148,699'Technique for calibrating electronic devices'20067,149,856'Method and apparatus for adjusting the performance of a synchronous memory system'20067,091,761'Impedance controlled output driver'20067,042,914'Calibrated data communication system and method'20067,039,782'Memory system with channel multiplexing of multiple memory devices'20067,039,147'Delay locked loop circuitry for clock delay adjustment'20066,990,042'Single-clock, strobeless signaling system'20066,987,823'System and method for aligning internal transmit and receive clocks'20066,982,922'Single-clock, strobeless signaling system'20066,975,956'Multiple sweep point testing of circuit devices'20056,963,956'Apparatus and method for pipelined memory operations'20056,950,956'Integrated circuit with timing adjustment mechanism and method'20056,934,201'Asynchronous, high-bandwidth memory component using calibrated timing elements'20056,931,467'Memory integrated circuit device which samples data upon detection of a strobe signal'20056,922,092'Impedance controlled output driver'20056,912,620'Memory device which receives write masking information'20056,889,304'Memory device supporting a dynamically configurable core organization'20056,868,474'High performance cost optimized memory'20056,810,449'Protocol for communication with dynamic memory'20046,801,099'Methods for bi-directional signaling'20046,788,593'Asynchronous, high-bandwidth memory component using calibrated timing elements'20046,788,594'Asynchronous, high-bandwidth memory component using calibrated timing elements'20046,757,789'Apparatus and method for maximizing information transfers over limited interconnect resources'20046,718,431'Apparatus and method for pipelined memory operations'20046,708,248'Memory system with channel multiplexing of multiple memory devices'20046,701,446'Power control system for synchronous memory device'20046,681,288'Memory device with receives write masking information'20046,661,268'Charge compensation control circuit and method for use with output driver'20036,646,953'Single-clock, strobeless signaling system'20036,643,787'Bus system optimization'20036,617,871'Methods and apparatus for bi-directional signaling'20036,591,353'Protocol for communication with dynamic memory'20036,574,153'Asynchronous, high-bandwidth memory component using calibrated timing elements'20036,553,452'Synchronous memory device having a temperature register'20036,539,072'Delay locked loop circuitry for clock delay adjustment'20036,513,103'Method and apparatus for adjusting the performance of a synchronous memory system'20036,496,897'Semiconductor memory device which receives write masking information'20026,493,789'Memory device which receives write masking and automatic precharge information'20026,470,405'Protocol for communication with dynamic memory'20026,448,828'Apparatus and method for edge based duty cycle conversion'20026,401,167'High performance cost optimized memory'20026,378,018'Memory device and system including a low power interface'20026,356,975'Apparatus and method for pipelined memory operations'20026,347,354'Apparatus and method for maximizing information transfers over limited interconnect resources'20026,342,800'Charge compensation control circuit and method for use with output driver'20026,323,706'Apparatus and method for edge based duty cycle conversion'2001RE037409'Memory and method for sensing sub-groups of memory elements'20016,266,737'Method and apparatus for providing a memory with write enable information'20016,263,448'Power control system for synchronous memory device'20016,226,757'Apparatus and method for bus timing compensation'20016,226,754'Apparatus and method for device timing compensation'20016,163,178'Impedance controlled output driver'20006,133,773'Variable delay element'20006,134,172'Apparatus for sharing sense amplifiers between memory banks'20006,125,157'Delay-locked loop circuitry for clock delay adjustment'20006,122,208'Circuit and method for column redundancy for high bandwidth memories'20006,122,688'Protocol for communication with dynamic memory'20006,075,730'High performance cost optimized memory with delayed memory writes'20006,075,743'Method and apparatus for sharing sense amplifiers between memory banks'20006,035,369'Method and apparatus for providing a memory with write enable information'20005,966,731'Protocol for communication with dynamic memory'19995,913,046'Protocol for communication with dynamic memory'19995,825,209'Quadrature phase detector'19985,748,914'Protocol for communication with dynamic memory'19985,748,554'Memory and method for sensing sub-groups of memory elements'19985,479,370'Semiconductor memory with bypass circuit'19955,410,512'Semiconductor memory device'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995Based in Zushi, JP· patent location history
1998–2019Patents assigned to RAMBUS INC (108)· patent assignee history
1998–2020Based in Palo Alto, CA, US· patent location history
1998–2007Based in Woodside, CA, US· patent location history
2000–2014Based in Los Altos, CA, US· patent location history
2000–2012Based in Los Altos Hills, CA, US· patent location history
2011–2014Patents assigned to STARK DONALD C (13)· patent assignee history
2011–2013Patents assigned to HAMPEL CRAIG E (8)· patent assignee history
2011–2013Patents assigned to TSERN ELY K (7)· patent assignee history
2011–2013Patents assigned to WARE FREDERICK A (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RAMBUS INC1081998–2019
STARK DONALD Cself132011–2014
HAMPEL CRAIG E82011–2013
TSERN ELY K72011–2013
WARE FREDERICK A62011–2013
Locations
LocationPatentsSpan
Los Altos, California, US432000–2014
Palo Alto, California, US311998–2020
Los Altos Hills, California, US282000–2012
Woodside, California, US151998–2007
Zushi, JP21995