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Inventor

Takuya Futase

Inventor
Tokyo, JP

Overview

34→
Patents
2003–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 34 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10DInorganic electric semiconductor devices20%
H10BElectronic memory devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H01LSemiconductor devices12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
C23FNon-mechanical removal of metallic material from surface4%
H10NElectric solid-state devices not otherwise provided for3%
C23CCoating metallic material2%
G11CStatic stores2%
PatentTitleYear
11,114,157Low resistance monosilicide electrode for phase change memory and methods of making the same202110,297,312Resistive memory cell programmed by metal alloy formation and method of operating thereof201910,096,654Three-dimensional resistive random access memory containing self-aligned memory elements20189,847,249Buried etch stop layer for damascene bit line formation20179,799,527'Double trench isolation'20179,768,183'Source line formation and structure'20179,607,997'Metal line with increased inter-metal breakdown voltage'20179,524,904'Early bit line air gap formation'20169,478,461'Conductive line structure with openings'20169,466,523'Contact hole collimation using etch-resistant walls'20169,443,910'Silicided bit line for reversible-resistivity memory'20169,401,305'Air gaps structures for damascene metal patterning'20169,391,081'Metal indentation to increase inter-metal breakdown voltage'20169,245,898'NAND flash memory integrated circuits and processes with controlled gate height'20169,177,853'Barrier layer stack for bit line air gap formation'20158,541,297'Manufacturing method of semiconductor device'20138,293,648'Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device'20128,278,199'Method of manufacturing a semiconductor device'20128,268,682'Method for manufacturing a semiconductor integrated circuit device'20128,222,133'Manufacturing method of semiconductor device'20128,110,457'Method of manufacturing semiconductor device'20128,039,378'Method of manufacturing a semiconductor device'20118,034,717'Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device'20118,021,979'Method of manufacturing semiconductor device'20117,994,049'Manufacturing method of semiconductor device including filling a connecting hole with metal film'20117,964,500'Method of manufacturing semiconductor integrated circuit device'20117,964,509'Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device'20117,955,925'Method of manufacturing semiconductor device'20117,923,319'Method for manufacturing a semiconductor integrated circuit device circuit device'20117,851,355'Method of manufacturing semiconductor device'20107,700,448'Manufacturing method of semiconductor device'20107,566,662'Method of dry cleaning silicon surface prior to forming self-aligned nickel silicide layer'20096,737,221'Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device'20046,586,161'Mass production method of semiconductor integrated circuit device and manufacturing method of electronic device'2003

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2003–2012Patents assigned to HITACHI ULSI SYS CO LTD (4)· patent assignee history
2003–2012Based in Fussa, JP· patent location history
2009–2012Based in Tokyo, JP· patent location history
2010–2013Patents assigned to RENESAS ELECTRONICS CORP (15)· patent assignee history
2012–2013Patents assigned to FUTASE TAKUYA (6)· patent assignee history
2015–2017Patents assigned to SANDISK TECHNOLOGIES INC (8)· patent assignee history
2015–2021Based in Nagoya, JP· patent location history
2016–2019Patents assigned to SANDISK TECHNOLOGIES LLC (11)· patent assignee history
2016–2019Based in Yokkaichi, JP· patent location history
2016Based in Mie, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
RENESAS ELECTRONICS CORP152010–2013
SANDISK TECHNOLOGIES LLC112016–2019
SANDISK TECHNOLOGIES INC82015–2017
FUTASE TAKUYAself62012–2013
HITACHI ULSI SYS CO LTD42003–2012
Locations
LocationPatentsSpan
Tokyo, JP132009–2012
Yokkaichi, JP82016–2019
Nagoya, JP52015–2021
Fussa, JP52003–2012
Mie, JP22016