Inventor
Drew E. Wingard
Inventor
Palo Alto, CA, US
Overview
Patents· 39 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing51%
H04LTransmission of digital information, e.g. telegraphic communication19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use16%
G11CStatic stores6%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications4%
G01RMeasuring electric variables1%
H04JMultiplex communication1%
PatentTitleYear
10,921,874Hardware-based operating point controller for circuit regions in an integrated circuit202110,901,490Operating point controller for circuit regions202110,664,421Reordering responses in a high performance on-chip network202010,303,628Reordering responses in a high performance on-chip network201910,152,112Power manager with a power switch arbitrator201810,062,422Various methods and apparatus for configurable mapping of address regions onto one or more aggregate targets20189,495,290'Various methods and apparatus to support outstanding requests to multiple targets while maintaining transaction ordering'20169,405,700'Methods and apparatus for virtualization in an integrated circuit'20169,292,436'Various methods and apparatus to support transactions whose data address sequence within that transaction crosses an interleaved channel address boundary'20168,972,995'Apparatus and methods to concurrently perform per-thread as well as per-tag memory access scheduling within a thread and across two or more threads'20158,868,941'Apparatus and methods for an interconnect power manager'20148,504,992'Method and apparatus for establishing a quality of service model'20138,484,397'Various methods and apparatus for a memory scheduler with an arbiter'20138,438,320'Various methods and apparatus for address tiling and channel interleaving throughout the integrated system'20138,407,433'Interconnect implementing internal controls'20138,229,723'Performance software instrumentation and analysis for electronic design automation'20128,190,804'Various methods and apparatus for a memory scheduler with an arbiter'20128,108,648'Various methods and apparatus for address tiling'20128,032,676'Methods and apparatuses to manage bandwidth mismatches between a sending device and a receiving device'20118,032,329'Method and system to monitor, debug, and analyze performance of an electronic design'20117,793,345'Method and apparatus for a configurable protection architecture for on-chip systems'20107,660,932'Composing on-chip interconnects with configurable interfaces'20107,647,441'Communications system and method with multilevel connection identification'20107,356,633'Composing on-chip interconnects with configurable interfaces'20087,325,221'Logic system with configurable interface'20087,302,691'Scalable low bandwidth multicast handling in mixed core systems'20077,296,105'Method and apparatus for configuring an interconnect to implement arbitration'20077,277,975'Methods and apparatuses for decoupling a request from one or more solicited responses'20077,266,786'Method and apparatus for configurable address mapping and protection architecture and hardware for on-chip systems'20077,254,603'On-chip inter-network performance optimization using configurable performance parameters'20077,194,566'Communication system and method with configurable posting points'20077,165,094'Communications system and method with non-blocking shared interface'20077,155,554'Methods and apparatuses for generating a single request for block transactions over a communication fabric'20067,120,712'Communications system and method with multilevel connection identification'20066,785,753'Method and apparatus for response modes in pipelined environment'20046,725,313'Communications system and method with multilevel connection identification'20046,330,225'Communication system and method for different quality of service guarantees for different data flows'20016,182,183'Communications system and method with multilevel connection identification'20015,948,089'Fully-pipelined fixed-latency communications system with a real time dynamic bandwidth allocation'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2019Patents assigned to SONICS INC (36)· patent assignee history
1999–2008Based in San Carlos, CA, US· patent location history
2010–2021Based in Palo Alto, CA, US· patent location history
2012–2016Patents assigned to WINGARD DREW E (11)· patent assignee history
2012–2016Patents assigned to CHOU CHIEN-CHUN (8)· patent assignee history
2012–2015Patents assigned to SRINIVASAN KRISHNAN (6)· patent assignee history
2013–2016Patents assigned to HAMILTON STEPHEN W (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SONICS INC | 36 | 1999–2019 |
| WINGARD DREW Eself | 11 | 2012–2016 |
| CHOU CHIEN-CHUN | 8 | 2012–2016 |
| SRINIVASAN KRISHNAN | 6 | 2012–2015 |
| HAMILTON STEPHEN W | 4 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Palo Alto, California, US | 23 | 2010–2021 |
| San Carlos, California, US | 16 | 1999–2008 |