Inventor
DANIEL CHANEMOUGAME
Inventor
US
Overview
Patents· 48 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices27%
H01LSemiconductor devices26%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
B82YSpecific uses or applications of nanostructures12%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
H10BElectronic memory devices4%
G11CStatic stores1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
H03KPulse technique1%
H10NElectric solid-state devices not otherwise provided for1%
PatentTitleYear
12,568,651Semiconductor structure having stacked gates and method of manufacture thereof202612,557,392Highly regular logic design for efficient 3D integration202612,557,377Inverted cross-couple for top-tier FET for multi-tier gate-on-gate 3DI202612,446,291Inverted top-tier FET for multi-tier gate-on-gate 3-dimension integration (3Di)202512,414,367Tapered device for lateral gate all around devices202512,354,991Replacement buried power rail in backside power delivery202512,336,274Self-aligned method for vertical recess for 3D device integration202512,237,333Power wall integration for multiple stacked devices202512,224,281Interdigitated device stack202512,218,135Wiring in diffusion breaks in an integrated circuit202512,218,066Monolithic formation of a set of interconnects below active devices202512,176,293Inter-tier power delivery network (PDN) for dense gate-on-gate 3D logic integration202412,131,994Metallization lines on integrated circuit products202412,087,640High density logic formation using multi-dimensional laser annealing202412,051,638Integrated high efficiency transistor cooling202412,040,271Power delivery network for CFET with buried power rails202412,020,990Method for threshold voltage tuning through selective deposition of high-k metal gate (HKMG) film stacks202412,002,869Gate contact structures and cross-coupled contact structures for transistor devices202412,002,862Inter-level handshake for dense 3D logic integration202411,961,802Power-tap pass-through to connect a buried power rail to front-side power distribution network202411,923,364Double cross-couple for two-row flip-flop using CFET202411,830,852Multi-tier backside power delivery network for dense gate-on-gate 3D logic202311,791,263Metallization lines on integrated circuit products202311,791,271Monolithic formation of a set of interconnects below active devices202311,764,266Three-dimensional semiconductor device202311,764,113Method of 3D logic fabrication to sequentially decrease processing temperature and maintain material thermal thresholds202311,735,525Power delivery network for CFET with buried power rails202311,723,187Three-dimensional memory cell structure202311,665,878CFET SRAM bit cell with two stacked device decks202311,646,318Connections from buried interconnects to device terminals in multiple stacked devices structures202311,631,6713D complementary metal oxide semiconductor (CMOS) device and method of forming the same202311,621,333Gate contact structure for a transistor device202311,605,672Steep-switch field effect transistor with integrated bi-stable resistive system202311,581,242Integrated high efficiency gate on gate cooling202311,574,845Apparatus and method for simultaneous formation of diffusion break, gate cut, and independent N and P gates for 3D transistor devices202311,545,497CFET SRAM bit cell with three stacked device decks202311,532,708Stacked three-dimensional field-effect transistors202211,488,947Highly regular logic design for efficient 3D integration202211,469,309Gate contact structures and cross-coupled contact structures for transistor devices202211,450,671Semiconductor apparatus having stacked devices and method of manufacture thereof202211,437,376Compact 3D stacked-CFET architecture for complex logic cells202211,342,4273D directed self-assembly for nanostructures202211,322,401Reverse contact and silicide process for three-dimensional semiconductor devices202211,264,289Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks202211,264,274Reverse contact and silicide process for three-dimensional logic devices202211,233,006Metallization lines on integrated circuit products202211,201,152Method, apparatus, and system for fin-over-nanosheet complementary field-effect-transistor202111,177,250Method for fabrication of high density logic and memory for advanced circuit architecture2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to TOKYO ELECTRON LTD (40)· patent assignee history
2021Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history
2021–2026Based in US· patent location history
2022–2024Patents assigned to GLOBALFOUNDRIES US INC (6)· patent assignee history
2023Patents assigned to IBM (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOKYO ELECTRON LTD | 40 | 2021–2026 |
| GLOBALFOUNDRIES US INC | 6 | 2022–2024 |
| GLOBALFOUNDRIES INC | 1 | 2021 |
| IBM | 1 | 2023 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 48 | 2021–2026 |