Inventor
Patrick Morrow
Inventor
Portland, OR, US
Overview
Patents· 96 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1024%
H01LSemiconductor devices23%
H10DInorganic electric semiconductor devices19%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10BElectronic memory devices5%
H05KPrinted circuits2%
B23KSoldering or unsoldering1%
G01RMeasuring electric variables1%
B82YSpecific uses or applications of nanostructures1%
G01NInvestigating or analysing materials by determining their chemical or physical properties1%
PatentTitleYear
11,107,811Metallization structures under a semiconductor device layer202111,107,924Systems and methods to reduce FinFET gate capacitance202111,094,672Composite IC chips including a chiplet embedded within metallization layers of a host IC chip202111,075,119Vertically stacked transistors in a pin202111,075,202Bottom fin trim isolation aligned with top gate for stacked device architectures202111,049,861Method, device and system to provide capacitance for a dynamic random access memory cell202111,037,916Apparatus with multi-wafer based device comprising embedded active devices and method for forming such202111,037,817Apparatus with multi-wafer based device and method for forming such202111,011,537Vertical interconnect methods for stacked device architectures using direct self assembly with high operational parallelization and improved scalability202110,998,302Packaged device with a chiplet comprising memory resources202110,978,590Methods and apparatus to remove epitaxial defects in semiconductors202110,944,399Multi-level spin logic202110,937,665Methods and apparatus for gettering impurities in semiconductors202110,910,405Backside fin recess control with multi-HSI option202110,896,847Techniques for revealing a backside of an integrated circuit device, and associated configurations202110,892,337Backside source/drain replacement for semiconductor devices with metallization on both sides202110,892,215Metal on both sides with power distributed through the silicon202110,886,217Integrated circuit device with back-side interconnection to deep source/drain semiconductor202110,872,820Integrated circuit structures202010,861,870Inverted staircase contact for density improvement to 3D stacked devices202010,847,635Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices202010,797,139Methods of forming backside self-aligned vias and structures formed thereby202010,784,358Backside contact structures and fabrication for metal on both sides of devices202010,763,248Multi-layer silicon/gallium nitride semiconductor202010,734,412Backside contact resistance reduction for semiconductor devices with metallization on both sides202010,714,446Apparatus with multi-wafer based device comprising embedded active and/or passive devices and method for forming such202010,700,039Silicon die with integrated high voltage devices202010,672,831High density memory architecture using back side metal layers202010,658,291Metal on both sides with clock gated-power and signal routing underneath202010,636,907Deep EPI enabled by backside reveal for stress enhancement and contact202010,600,810Backside fin recess control with multi-hsi option202010,529,827Long channel MOS transistors for low leakage applications on a short channel CMOS chip202010,522,510Heterogeneous integration of ultrathin functional block by solid phase adhesive and selective transfer201910,490,449Techniques for revealing a backside of an integrated circuit device, and associated configurations201910,490,542Integrated circuit layout using library cells with alternating conductive lines201910,483,321High density memory architecture using back side metal layers201910,468,489Isolation structures for an integrated circuit element and method of making same201910,453,679Methods and devices integrating III-N transistor circuitry with Si transistor circuitry201910,439,057Multi-gate high electron mobility transistors and methods of fabrication201910,396,045Metal on both sides of the transistor integrated with magnetic inductors201910,367,070Methods of forming backside self-aligned vias and structures formed thereby201910,361,090Vertical channel transistors fabrication process by selective subtraction of a regular grid201910,325,840Metal on both sides with power distributed through the silicon201910,304,946Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices201910,297,592Monolithic three-dimensional (3D) ICs with local inter-level interconnects201910,236,282Partial layer transfer system and method201910,186,484Metal on both sides with clock gated-power and signal routing underneath201910,068,874Method for direct integration of memory die to logic die without use of thru silicon vias (TSV)201810,043,797Techniques for forming vertical transistor architectures201810,014,374Planar heterogeneous device20189,935,191High electron mobility transistor fabrication process on reverse polarized substrate by layer transfer20189,818,751'Methods of forming buried vertical capacitors and structures formed thereby'20179,793,373'Field effect transistor structure with abrupt source/drain junctions'20179,761,514'Substrate for integrated circuit devices including multi-layer glass core and methods of making the same'20179,721,898'Methods of forming under device interconnect structures'20179,685,436'Monolithic three-dimensional (3D) ICs with local inter-level interconnects'20179,646,972'Methods of forming buried vertical capacitors and structures formed thereby'20179,640,634'Field effect transistor structure with abrupt source/drain junctions'20179,590,051'Heterogeneous layer device'20179,490,201'Methods of forming under device interconnect structures'20169,461,010'Debond interconnect structures'20169,420,707'Substrate for integrated circuit devices including multi-layer glass core and methods of making the same'20169,269,686'Debond interconnect structures'20169,177,831'Die assembly on thin dielectric sheet'20158,637,778'Debond interconnect structures'20148,421,225'Three-dimensional stacked substrate arrangements'20138,203,208'Three-dimensional stacked substrate arrangements'20127,973,407'Three-dimensional stacked substrate arrangements'20117,800,371'Portable NMR device and method for making and using the same'20107,755,124'Laminating magnetic materials in a semiconductor device'20107,745,940'Forming ultra dense 3-D interconnect structures'20107,723,759'Stacked wafer or die packaging with enhanced thermal and device performance'20107,682,916'Field effect transistor structure with abrupt source/drain junctions'20107,436,035'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20087,410,884'3D integrated circuits using thick metal for backside connections and offset bumps'20087,402,509'Method of forming self-passivating interconnects and resulting devices'20087,391,087'MOS transistor structure and method of fabrication'20087,345,479'Portable NMR device and method for making and using the same'20087,338,873'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20087,274,191'Integrated on-chip NMR and ESR device and method for making and using the same'20077,217,595'Sealed three dimensional metal bonded integrated circuits'20077,214,605'Deposition of diffusion barrier'20077,214,594'Method of making semiconductor device using a novel interconnect cladding layer'20077,180,180'Stacked device underfill and a method of fabrication'20077,129,172'Bonded wafer processing method'20067,056,813'Methods of forming backside connections on a wafer stack'20066,992,391'Dual-damascene interconnects without an etch stop layer by alternating ILDs'20066,946,384'Stacked device underfill and a method of fabrication'20056,897,125'Methods of forming backside connections on a wafer stack'20056,887,762'Method of fabricating a field effect transistor structure with abrupt source/drain junctions'20056,872,666'Method for making a dual damascene interconnect using a dual hard mask'20056,797,556'MOS transistor structure and method of fabrication'20046,661,094'Semiconductor device having a dual damascene interconnect spaced from a support structure'20036,541,343'Methods of making field effect transistor structure with partially isolated source/drain junctions'20036,479,391'Method for making a dual damascene interconnect using a multilayer hard mask'20026,448,177'Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2021Patents assigned to INTEL CORP (96)· patent assignee history
2002–2021Based in Portland, OR, US· patent location history
2012–2019Patents assigned to MORROW PATRICK (8)· patent assignee history
2012–2019Patents assigned to KOBRINSKY MAURO J (3)· patent assignee history
2014–2019Patents assigned to FISCHER PAUL B (3)· patent assignee history
2014–2016Patents assigned to MA QING (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 96 | 2002–2021 |
| MORROW PATRICKself | 8 | 2012–2019 |
| FISCHER PAUL B | 3 | 2014–2019 |
| KOBRINSKY MAURO J | 3 | 2012–2019 |
| MA QING | 3 | 2014–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Portland, OR, US | 96 | 2002–2021 |