Inventor
Luiz M. Franca-Neto
Inventor
Sunnyvale, CA, US
Overview
Patents· 89 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores18%
H10NElectric solid-state devices not otherwise provided for13%
H10BElectronic memory devices11%
H01LSemiconductor devices10%
G06FElectric digital data processing9%
G11BInformation storage based on relative movement between record carrier and transducer7%
H03FAmplifiers5%
H10DInorganic electric semiconductor devices3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H04BTransmission2%
PatentTitleYear
10,860,477Apparatus and method for low power low latency high capacity storage class memory202010,796,198Adjusting enhancement coefficients for neural network engine202010,644,958All-connected by virtual wires network of data processing nodes202010,514,867System and methodology that facilitates error management within a shared non-volatile memory architecture201910,460,801Multi-level phase change device201910,361,365Implementing deposition growth method for magnetic memory201910,283,562Process for fabricating three dimensional non-volatile memory system201910,254,982System and methodology for low latency error management within a shared non-volatile memory architecture201910,249,682Non-volatile memory system with serially connected non-volatile reversible resistance-switching memory cells201910,229,737Non-volatile memory with adjustable cell bit shape201910,222,992Synchronization method and apparatus for an interconnection network using parallel-headerless TDMA routing201910,217,505Chip with phase change memory and magnetoresistive random access memory201910,216,571System and methodology for error management within a shared non-volatile memory architecture using bloom filters201910,217,795Memory cell for non-volatile memory system201910,163,504Planar variable resistance memory201810,157,656Implementing enhanced magnetic memory cell201810,109,681Vertical memory structure with array interconnects and method for producing the same201810,020,053Multi-level phase change device20189,899,595'Implementing deposition growth method for magnetic memory'20189,780,143'Implementing magnetic memory integration with CMOS driving circuits'20179,741,769'Vertical memory structure with array interconnects and method for producing the same'20179,728,255'Planar variable resistance memory'20179,673,387'Implementing magnetic memory pillar design'20179,564,585'Multi-level phase change device'20179,520,444'Implementing magnetic memory pillar design'20169,472,281'Non-volatile memory with adjustable cell bit shape'20169,443,905'Implementing 3D scalable magnetic memory with interlayer dielectric stack and pillar holes having programmable area'20169,444,036'Implementing segregated media based magnetic memory'20169,438,576'Apparatus and method for validation and authorization of device and user by global positioning and non-prompted exchange of information'20169,431,457'Implementing deposition growth method for magnetic memory'20169,367,483'Acoustically secure phase change memory devices'20169,356,001'Semiconductor device with at least one voltage-guided conductive filament'20169,274,884'Encoding and decoding data to accommodate memory cells having stuck-at faults'20169,208,871'Implementing enhanced data read for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding'20159,153,290'Intra-zone wear leveling for heat-assisted magnetic recording—shingled magnetic recording (HAMR-SMR) type storage devices'20159,070,483'Encoding and decoding redundant bits to accommodate memory cells having stuck-at faults'20158,996,955'Techniques for storing data in stuck and unstable memory cells'20158,988,918'High current capable access device for three-dimensional solid-state memory'20158,943,388'Techniques for encoding and decoding using a combinatorial number system'20158,887,025'Techniques for storing data in stuck memory cells'20148,812,934'Techniques for storing bits in memory cells having stuck-at faults'20148,792,272'Implementing enhanced data partial-erase for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding'20148,767,431'High current capable access device for three-dimensional solid-state memory'20148,711,597'3D solid-state arrangement for solid state memory'20148,699,266'Implementing enhanced data write for multi-level cell (MLC) memory using threshold voltage-drift or resistance drift tolerant moving baseline memory data encoding'20148,649,215'Data management in flash memory using probability of charge disturbances'20148,638,527'Signaling method and apparatus for write assist of high coercivity media using integrated half coil'20148,599,609'Data management in flash memory using probability of charge disturbances'20138,587,900'Radiator-cooled nanowire-based write assist'20138,422,303'Early degradation detection in flash memory using test cells'20138,422,296'Early detection of degradation in NAND flash memory'20138,411,390'Integrated half coil structure for write assist of high coercivity media'20138,374,558'Antenna array with flexible interconnect for a mobile wireless device'20138,369,143'Early detection of degradation in NOR flash memory'20138,305,712'Tunable microstrip signal transmission path in a hard disk drive'20128,233,240'Magnetic recording disk drive with integrated lead suspension having multiple segments for optimal characteristic impedance'20128,154,827'Integrated lead suspension with multiple crossover coplanar connection of the electrically conductive traces'20128,107,177'Electrical interconnect system with integrated transmission- line compensation components'20128,085,490'Slider fly-height control in a hard disk drive'20118,049,984'Integrated slider bias control'20118,045,297'Flex cable and method for lowering flex cable impedance'20117,830,634'Head-disk contact detection and work function difference determination'20107,786,754'High speed digital signaling apparatus and method using reflected signals to increase total delivered current'20107,719,786'Active fly height control using radio frequency feedback'20107,660,068'Method and system for pre-contact detection and active damping of air bearing vibrations in a hard disk drive'20107,519,344'Bandpass amplifier, method, and system'20097,415,245'Pulse shaping signals for ultrawideband communication'20087,383,058'RF/microwave system with a system on a chip package or the like'20087,233,780'Method and apparatus for performing DC offset cancellation in a receiver'20077,151,810'Data and clock synchronization in multi-channel communications'20067,069,042'Quadrature direct synthesis discrete time multi-tone generator'20067,049,855'Area efficient waveform evaluation and DC offset cancellation circuits'20066,982,879'Apparatus to provide connection between a microelectronic device and an antenna'20066,838,944'Receiver system with electrically tuned integrated amplifier and method'20056,806,777'Ultra wide band low noise amplifier and method'20046,721,544'Duplexer structure for coupling a transmitter and a receiver to a common antenna'20046,714,054'Area efficient waveform evaluation and DC offset cancellation circuits'20046,707,343'Frequency synthesis apparatus, systems, and methods'20046,697,611'Method and apparatus for performing DC offset cancellation in a receiver'20046,690,239'High bandwidth, low power, single stage cascode transimpedance amplifier for short haul optical links'20046,654,846'High speed computer bus system with bi-directional transmission medium and interface device'20036,653,904'Electrically tuned integrated amplifier for wireless communications'20036,639,472'High bandwidth, low power, single stage cascode transimpedance amplifier for short haul optical links'20036,608,529'Frequency synthesis apparatus, systems, and methods'20036,509,799'Electrically tuned integrated amplifier for wireless communications'20036,507,915'Clock and data signal separator circuit'20036,466,775'Radio-frequency mixer for wireless applications'20026,445,220'Method and apparatus for fully-differential half-circulator for bi-directional small-signal signaling'20026,429,742'Gain-controlled tuned differential adder'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2009Patents assigned to INTEL CORP (24)· patent assignee history
2002–2008Based in Hillsboro, OR, US· patent location history
2008–2009Based in Portland, OR, US· patent location history
2010–2020Based in Sunnyvale, CA, US· patent location history
2010Based in Santa Clara, CA, US· patent location history
2011–2016Patents assigned to FRANCA-NETO LUIZ M (18)· patent assignee history
2011–2014Patents assigned to HITACHI GLOBAL STORAGE TECH NL (9)· patent assignee history
2013–2020Patents assigned to HGST Netherlands BV (31)· patent assignee history
2016–2020Patents assigned to WESTERN DIGITAL TECH INC (18)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| HGST Netherlands BV | 31 | 2013–2020 |
| INTEL CORP | 24 | 2002–2009 |
| FRANCA-NETO LUIZ Mself | 18 | 2011–2016 |
| WESTERN DIGITAL TECH INC | 18 | 2016–2020 |
| HITACHI GLOBAL STORAGE TECH NL | 9 | 2011–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sunnyvale, California, US | 63 | 2010–2020 |
| Hillsboro, OR, US | 22 | 2002–2008 |
| Santa Clara, California, US | 2 | 2010 |
| Portland, OR, US | 2 | 2008–2009 |