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Inventor

Todd Michael Austin

Inventor
Ann Arbor, MI, US

Overview

27→
Patents
1995–2020
Patent span
Physics
Primary field (CPC G)

Patents· 27 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing63%
G11CStatic stores18%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use15%
H03KPulse technique3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
10,579,463Error recovery within integrated circuit202010,572,334Error recovery within integrated circuit20209,645,882'Field repairable logic'20179,448,875'Error recovery within integrated circuit'20169,164,842'Error recovery within integrated circuit'20158,650,470'Error recovery within integrated circuit'20148,407,537'Error recover within processing stages of an integrated circuit'20138,341,473'Microprocessor and method for detecting faults therein'20128,185,786'Error recovery within processing stages of an integrated circuit'20128,060,814'Error recovery within processing stages of an integrated circuit'20118,051,368'Microprocessor and method for detecting faults therein'20117,966,538'Microprocessor and method for detecting faults therein'20117,701,240'Integrated circuit with error correction mechanisms to offset narrow tolerancing'20107,650,551'Error detection and recovery within processing stages of an integrated circuit'20107,598,766'Customized silicon chips produced using dynamically configurable polymorphic network'20097,475,394'System and method of analyzing interpreted programs'20097,401,273'Recovery from errors in a data processing apparatus'20087,398,375'Technique for reduced-tag dynamic scheduling and reduced-tag prediction'20087,337,356'Systematic and random error detection and recovery within processing stages of an integrated circuit'20087,310,755'Data retention latch provision within integrated circuits'20077,278,080'Error detection and recovery within processing stages of an integrated circuit'20077,162,661'Systematic and random error detection and recovery within processing stages of an integrated circuit'20077,072,229'Memory system having fast and slow data reading mechanisms'20066,944,067'Memory system having fast and slow data reading mechanisms'20055,860,151'Data cache fast address calculation system and method'19995,644,709'Method for detecting computer memory access errors'19975,420,696'Image data transfer architecture and method for an electronic reprographic machine'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–1999Based in Madison, WI, US· patent location history
2005–2015Patents assigned to UNIV MICHIGAN (17)· patent assignee history
2005–2020Patents assigned to ADVANCED RISC MACH LTD (15)· patent assignee history
2005–2020Based in Ann Arbor, MI, US· patent location history
2011–2017Patents assigned to AUSTIN TODD MICHAEL (6)· patent assignee history
2011–2014Patents assigned to BLAAUW DAVID THEODORE (4)· patent assignee history
2016–2020Patents assigned to UNIV MICHIGAN REGENTS (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
UNIV MICHIGAN172005–2015
ADVANCED RISC MACH LTD152005–2020
AUSTIN TODD MICHAELself62011–2017
BLAAUW DAVID THEODORE42011–2014
UNIV MICHIGAN REGENTS42016–2020
Locations
LocationPatentsSpan
Ann Arbor, MI, US242005–2020
Madison, WI, US31995–1999