Inventor
Alexander F. Heinecke
Inventor
San Jose, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing66%
G06NComputing arrangements based on specific computational models17%
G06TImage data processing or generation, in general5%
G06KGraphical data reading2%
G06VImage or video recognition or understanding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H04WWireless communication networks2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
11,126,428Computer processor for higher precision computations using a mixed-precision decomposition of operations202111,093,247Systems and methods to load a tile register pair202111,080,048Systems, methods, and apparatus for tile configuration202111,068,263Systems and methods for performing instructions to convert to 16-bit floating-point format202111,068,262Systems and methods for performing instructions to convert to 16-bit floating-point format202111,036,504Systems and methods for performing 16-bit floating-point vector dot product instructions202111,023,235Systems and methods to zero a tile register pair202110,990,396Systems for performing instructions to quickly convert and use tiles as 1D vectors202110,970,072Systems and methods to transpose vectors on-the-fly while loading from memory202110,970,076Systems and methods for performing instructions specifying ternary tile logic operations202110,963,246Systems and methods for performing 16-bit floating-point matrix dot product instructions202110,963,256Systems and methods for performing instructions to transform matrices into row-interleaved format202110,956,298Methods and apparatus to detect memory leaks in computing systems202110,929,143Method and apparatus for efficient matrix alignment in a systolic array202110,896,043Systems for performing instructions for fast element unpacking into 2-dimensional registers202110,877,756Systems, methods, and apparatuses for tile diagonal202010,866,786Systems and methods for performing instructions to transpose rectangular tiles202010,853,067Computer processor for higher precision computations using a mixed-precision decomposition of operations202010,853,554Systems and methods for determining a configuration for a microarchitecture202010,838,734Apparatus and method for processing structure of arrays (SoA) and array of structures (AoS) data202010,802,942Methods and apparatus to detect anomalies of a monitored system202010,776,699Optimized compute hardware for machine learning operations202010,719,323Systems and methods for performing matrix compress and decompress instructions202010,664,287Systems and methods for implementing chained tile operations202010,656,944Hardware apparatus and methods to prefetch a multidimensional block of elements from a multidimensional array202010,496,410Instruction and logic for suppression of hardware prefetchers20199,996,350Hardware apparatuses and methods to prefetch a multidimensional block of elements from a multidimensional array2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to INTEL CORP (27)· patent assignee history
2018–2021Based in San Jose, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 27 | 2018–2021 |