Inventor
Dina H. Triyoso
Inventor
Austin, TX, US
Overview
Patents· 34 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices38%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%
H01LSemiconductor devices14%
C23CCoating metallic material6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10BElectronic memory devices3%
B82YSpecific uses or applications of nanostructures1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
G06FElectric digital data processing1%
G21KHandling of particles or ionising radiation not otherwise provided for1%
PatentTitleYear
10,236,343Strain retention semiconductor member for channel SiGe layer of pFET201910,109,492Method of forming a high quality interfacial layer for a semiconductor device by performing a low temperature ALD process201810,050,119Method for late differential SOI thinning for improved FDSOI performance and HCI optimization20189,917,016'Integrated circuits and methods of forming the same with effective dummy gate cap removal'20189,583,557'Integrated circuits including a MIMCAP device and methods of forming the same for long and controllable reliability lifetime'20179,530,833'Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof'20169,466,661'Method of fabricating a MIM capacitor with minimal voltage coefficient and a decoupling MIM capacitor and analog/RF MIM capacitor on the same chip with high-K dielectrics'20169,362,284'Threshold voltage control for mixed-type non-planar semiconductor devices'20169,318,315'Complex circuit element and capacitor utilizing CMOS compatible antiferroelectric high-k materials'20169,269,785'Semiconductor device with ferroelectric hafnium oxide and method for forming semiconductor device'20169,209,186'Threshold voltage control for mixed-type non-planar semiconductor devices'20158,791,003'Methods for fabricating integrated circuits with fluorine passivation'20148,716,149'Methods for fabricating integrated circuits having improved spacers'20148,652,890'Methods for fabricating integrated circuits with narrow, metal filled openings'20148,420,519'Methods for fabricating integrated circuits with controlled P-channel threshold voltage'20138,404,594'Reverse ALD'20138,383,473'Methods of forming replacement gate structures for semiconductor devices'20138,039,386'Method for forming a through silicon via (TSV)'20118,030,220'Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer'20117,911,002'Semiconductor device with selectively modulated gate work function'20117,776,731'Method of removing defects from a dielectric material in a semiconductor'20107,704,821'In-situ nitridation of high-k dielectrics'20107,659,156'Method to selectively modulate gate work function through selective Ge condensation and high-K dielectric layer'20107,618,902'Plasma treatment of a semiconductor surface for enhanced nucleation of a metal-containing layer'20097,303,983'ALD gate electrode'20077,297,586'Gate dielectric and metal gate integration'20077,230,264'Semiconductor transistor having structural elements of differing materials'20077,132,360'Method for treating a semiconductor surface to form a metal-containing layer'20067,091,568'Electronic device including dielectric layer, and a process for forming the electronic device'20067,071,038'Method of forming a semiconductor device having a dielectric layer with high dielectric constant'20067,015,153'Method for forming a layer using a purging gas in a semiconductor process'20066,987,063'Method to reduce impurity elements during semiconductor film deposition'20066,979,622'Semiconductor transistor having structural elements of differing materials and method of formation'20056,835,671'Method of making an integrated circuit using an EUV mask formed by atomic layer deposition'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2013Patents assigned to FREESCALE SEMICONDUCTOR INC (18)· patent assignee history
2004Based in Houston, TX, US· patent location history
2005–2013Based in Austin, TX, US· patent location history
2013–2019Patents assigned to GLOBALFOUNDRIES INC (16)· patent assignee history
2013–2014Patents assigned to TRIYOSO DINA (4)· patent assignee history
2013–2014Patents assigned to ERBEN ELKE (3)· patent assignee history
2013–2018Based in Dresden, DE· patent location history
2014Patents assigned to BINDER ROBERT (2)· patent assignee history
2015–2019Based in Mechanicville, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 18 | 2004–2013 |
| GLOBALFOUNDRIES INC | 16 | 2013–2019 |
| TRIYOSO DINAself | 4 | 2013–2014 |
| ERBEN ELKE | 3 | 2013–2014 |
| BINDER ROBERT | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 17 | 2005–2013 |
| Dresden, DE | 9 | 2013–2018 |
| Mechanicville, New York, US | 7 | 2015–2019 |
| Houston, Texas, US | 1 | 2004 |