LexDanaLexDanabeta
Inventor

James Schleicher

Inventor
Los Gatos, CA, US

Overview

58→
Patents
1995–2020
Patent span
Electricity
Primary field (CPC H)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique54%
G06FElectric digital data processing46%
PatentTitleYear
10,803,225Peripheral tool202010,177,766Omnibus logic element20199,705,506'Field programmable gate array with integrated application specific integrated circuit fabric'20179,496,875'Omnibus logic element'20168,878,567'Omnibus logic element'20148,612,772'Security core using soft key'20138,593,174'Omnibus logic element for packing or fracturing'20138,314,636'Field programmable gate array with integrated application specific integrated circuit fabric'20128,237,465'Omnibus logic element for packing or fracturing'20128,099,694'Interactive tool for contemporaneous design of integrated circuits having different device packages'20127,911,230'Omnibus logic element for packing or fracturing'20117,877,721'Methods for producing equivalent field-programmable gate arrays and structured application-specific integrated circuits'20117,839,167'Interconnection and input/output resources for programmable logic integrated circuit devices'20107,812,633'Apparatus and method for the arithmetic over-ride of look up table outputs in a programmable logic device'20107,724,032'Field programmable gate array with integrated application specific integrated circuit fabric'20107,671,625'Omnibus logic element'20107,594,208'Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage'20097,587,686'Clock gating in a structured ASIC'20097,565,388'Logic cell supporting addition of three binary words'20097,538,579'Omnibus logic element'20097,492,188'Interconnection and input/output resources for programmable logic integrated circuit devices'20097,439,769'Programming logic device and method for programming the same'20087,420,390'Method and apparatus for implementing additional registers in field programmable gate arrays to reduce design size'20087,373,631'Methods of producing application-specific integrated circuit equivalents of programmable logic'20087,368,942'Dedicated resource interconnects'20087,360,197'Methods for producing equivalent logic designs for FPGAs and structured ASIC devices'20087,346,860'User non-volatile memory interface megafunction'20087,330,052'Area efficient fractureable logic elements'20087,317,332'Interconnection and input/output resources for programmable logic integrated circuit devices'20087,275,232'Methods for producing equivalent field-programmable gate arrays and structured application specific integrated circuits'20077,262,635'Interconnection resources for programmable logic integrated circuit devices'20077,205,791'Bypass-able carry chain in a programmable logic device'20077,181,703'Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usage'20077,167,022'Omnibus logic element including look up table based logic elements'20077,123,052'Interconnection resources for programmable logic integrated circuit devices'20067,119,575'Logic cell with improved multiplexer, barrel shifter, and crossbarring efficiency'20067,061,268'Initializing a carry chain in a programmable logic device'20067,030,652'LUT-based logic element with support for Shannon decomposition and associated method'20066,989,689'Interconnection and input/output resources for programmable logic integrated circuit devices'20066,897,680'Interconnection resources for programmable logic integrated circuit devices'20056,894,533'Interconnection and input/output resources for programmable logic integrated circuit devices'20056,879,183'Programmable logic device architectures with super-regions having logic regions and a memory region'20056,747,480'Programmable logic devices with bidirect ional cascades'20046,727,727'Interconnection resources for programmable logic integrated circuit devices'20046,614,261'Interconnection and input/output resources for programable logic integrated circuit devices'20036,525,564'Interconnection resources for programmable logic integrated circuit devices'20036,480,028'Programmable logic device architectures with super-regions having logic regions and memory region'20026,407,576'Interconnection and input/output resources for programmable logic integrated circuit devices'20026,366,120'Interconnection resources for programmable logic integrated circuit devices'20026,362,646'Method and apparatus for reducing memory resources in a programmable logic device'20026,265,895'Programmable logic device incorporating a memory efficient interconnection device'20016,263,482'Programmable logic device having macrocells with selectable product-term inversion'20016,215,326'Programmable logic device architecture with super-regions having logic regions and a memory region'20016,173,245'Programmable logic array device design using parameterized logic modules'20016,057,707'Programmable logic device incorporating a memory efficient interconnection device'20006,028,809'Programmable logic device incorporating a tristateable logic array block'20005,574,893'Computer logic simulation with dynamic modeling'19965,477,474'Computer logic simulation with dynamic modeling'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2019Patents assigned to ALTERA CORP (57)· patent assignee history
1995–2002Based in Sunnyvale, CA, US· patent location history
2001–2010Based in Santa Clara, CA, US· patent location history
2006–2020Based in Los Gatos, CA, US· patent location history
2012–2017Patents assigned to SCHLEICHER II JAMES G (4)· patent assignee history
2012–2013Patents assigned to BAECKLER GREGG (2)· patent assignee history
2012–2017Patents assigned to HUTTON MICHAEL D (2)· patent assignee history
2012–2013Patents assigned to HUTTON MIKE (2)· patent assignee history
2014–2019Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP571995–2019
SCHLEICHER II JAMES Gself42012–2017
BAECKLER GREGG22012–2013
HUTTON MICHAEL D22012–2017
HUTTON MIKE22012–2013
Locations
LocationPatentsSpan
Los Gatos, California, US252006–2020
Santa Clara, California, US222001–2010
Sunnyvale, California, US81995–2002
San Jose, California, US32014–2019