Inventor
Panayotis C. Andricacos
Inventor
Croton-on-Hudson, NY, US
Overview
Patents· 52 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1020%
C25DProcesses for the electrolytic or electrophoretic production of coatings18%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10DInorganic electric semiconductor devices9%
Y10TTechnical subjects covered by former us classification7%
H01HElectric switches4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
C23CCoating metallic material3%
H10BElectronic memory devices3%
G11BInformation storage based on relative movement between record carrier and transducer3%
PatentTitleYear
7,829,427'Method of fabricating a high Q factor integrated circuit inductor'20107,678,258'Void-free damascene copper deposition process and means of monitoring thereof'20107,638,406'Method of fabricating a high Q factor integrated circuit inductor'20097,581,314'Method of forming noble metal contacts'20097,553,400'Plating apparatus and plating method'20097,227,265'Electroplated copper interconnection structure, process for making and electroplating bath'20077,212,091'Micro-electro-mechanical RF switch'20077,202,764'Noble metal contacts for micro-electromechanical switches'20077,190,079'Selective capping of copper wiring'20077,112,851'Field effect transistor with electroplated metal gate'20067,068,138'High Q factor integrated circuit inductor'20067,060,624'Deep filled vias'20067,008,871'Selective capping of copper wiring'20066,992,389'Barrier for interconnect and method'20066,979,393'Method for plating copper conductors and devices formed'20056,974,531'Method for electroplating on resistive substrates'20056,967,131'Field effect transistor with electroplated metal gate'20056,946,716'Electroplated interconnection structures on integrated circuit chips'20056,911,229'Structure comprising an interlayer of palladium and/or platinum and method for fabrication thereof'20056,876,282'Micro-electro-mechanical RF switch'20056,776,885'Integrated plating and planarization apparatus having a variable-diameter counterelectrode'20046,709,562'Method of making electroplated interconnection structures on integrated circuit chips'20046,639,488'MEMS RF switch with low actuation voltage'20036,589,874'Method for forming electromigration-resistant structures by doping'20036,570,255'Method for forming interconnects on semiconductor substrates and structures formed'20036,471,845'Method of controlling chemical bath composition in a manufacturing environment'20026,429,523'Method for forming interconnects on semiconductor substrates and structures formed'20026,416,812'Method for depositing copper onto a barrier layer'20026,406,608'Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal'20026,395,164'Copper seed layer repair technique using electroless touch-up'20026,391,773'Method and materials for through-mask electroplating and selective base removal'20026,344,129'Method for plating copper conductors and devices formed'20026,331,237'Method of improving contact reliability for electroplating'20016,323,127'Capacitor formed with Pt electrodes having a 3D cup-like shape with roughened inner and outer surfaces'20016,268,291'Method for forming electromigration-resistant structures by doping'20016,251,251'Anode design for semiconductor deposition'20016,224,690'Flip-Chip interconnections using lead-free solders'20016,188,120'Method and materials for through-mask electroplating and selective base removal'20016,113,769'Apparatus to monitor and add plating solution of plating baths and controlling quality of deposited metal'20006,090,710'Method of making copper alloys for chip and package interconnections'20006,063,506'Copper alloys for chip and package interconnections'20005,998,250'Compound electrode stack capacitor'19995,937,320'Barrier layers for electroplated SnPb eutectic solder joints'19995,825,609'Compound electrode stack capacitor'19985,789,320'Plating of noble metal electrodes for DRAM and FRAM'19985,582,927'High magnetic moment materials and process for fabrication of thin film heads'19965,522,975'Electroplating workpiece fixture'19965,516,412'Vertical paddle plating cell'19965,385,661'Acid electrolyte solution and process for the electrodeposition of copper-rich alloys exploiting the phenomenon of underpotential deposition'19955,352,350'Method for controlling chemical species concentration'19945,312,532'Multi-compartment eletroplating system'19945,132,859'Thin film structures for magnetic recording heads'1992Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1992–2010Patents assigned to IBM (52)· patent assignee history
1992–2010Based in Croton-on-Hudson, NY, US· patent location history
2002Patents assigned to NOVELLUS SYSTEMS INC (1)· patent assignee history
2009Patents assigned to EBARA CORP (1)· patent assignee history
2009Based in Yorktown Heights, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 52 | 1992–2010 |
| EBARA CORP | 1 | 2009 |
| NOVELLUS SYSTEMS INC | 1 | 2002 |
Locations
| Location | Patents | Span |
|---|---|---|
| Croton-on-Hudson, New York, US | 51 | 1992–2010 |
| Yorktown Heights, New York, US | 1 | 2009 |