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Inventor

Katsuyoshi Mitsui

Inventor
Hyogo, JP

Overview

35→
Patents
1991–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 35 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores24%
H10DInorganic electric semiconductor devices18%
G05FSystems for regulating electric or magnetic variables16%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses8%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems6%
H03BGeneration of oscillations, directly or by frequency-changing, by circuits employing active elements which operate in a non-switching manner6%
C23CCoating metallic material4%
H10BElectronic memory devices4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
PatentTitleYear
9,467,090'Semiconductor device'20168,963,650'Semiconductor device having on-chip oscillator for producing clock signal'20158,264,294'Semiconductor device having on-chip oscillator for producing clock signal'20127,728,678'Semiconductor device outputting oscillation signal'20106,937,088'Potential generating circuit capable of correctly controlling output potential'20056,812,748'Semiconductor device having substrate potential detection circuit less influenced by change in manufacturing conditions'20046,781,443'Potential generating circuit capable of correctly controlling output potential'20046,765,432'Semiconductor device with a low-power operation mode'20046,753,720'Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor'20046,714,065'Semiconductor device including power supply circuit conducting charge pumping operation'20046,603,695'Semiconductor memory device having self-refresh mode'20036,492,863'Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor'20026,377,074'Semiconductor device having a constant-current source circuit'20026,333,880'Semiconductor memory device capable of detecting high-voltage test command signal'20016,320,810'Semiconductor memory device allowing reduction in current consumption'20016,297,624'Semiconductor device having an internal voltage generating circuit'20016,262,931'Semiconductor memory device having voltage down convertor reducing current consumption'20016,229,753'Semiconductor memory device capable of accurate control of internally produced power supply potential'20016,201,437'Internal high voltage generation circuit capable of stably generating internal high voltage and circuit element therefor'20016,195,298'Semiconductor integrated circuit capable of rapidly rewriting data into memory cells'20016,121,806'Circuit for adjusting a voltage level in a semiconductor device'20006,091,648'Voltage generating circuit for semiconductor integrated circuit device'20005,999,009'Semiconductor integrated circuit with an internal voltage generating circuit requiring a reduced occupied area'19995,480,838'Method of manufacturing a semiconductor device having vertical transistor with tubular double-gate'19965,407,867'Method of forming a thin film on surface of semiconductor substrate'19955,382,816'Semiconductor device having vertical transistor with tubular double-gate'19955,378,923'Semiconductor device including a field effect transistor'19955,296,401'MIS device having p channel MOS device and n channel MOS device with LDD structure and manufacturing method thereof'19945,217,913'Method of manufacturing an MIS device having lightly doped drain structure and conductive sidewall spacers'19935,217,910'Method of fabricating semiconductor device having sidewall spacers and oblique implantation'19935,183,771'Method of manufacturing LDDFET having double sidewall spacers'19935,174,881'Apparatus for forming a thin film on surface of semiconductor substrate'19925,146,291'MIS device having lightly doped drain structure'19925,089,865'MIS semiconductor device'19925,075,240'Semiconductor device manufactured by using conductive ion implantation mask'1991

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1991–2003Patents assigned to MITSUBISHI ELECTRIC CORP (23)· patent assignee history
1991–2005Based in Hyogo, JP· patent location history
2000–2010Based in Tokyo, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (7)· patent assignee history
2012–2016Patents assigned to RENESAS ELECTRONICS CORP (3)· patent assignee history
2012–2015Patents assigned to MITSUI KATSUYOSHI (2)· patent assignee history
2012–2015Patents assigned to OISHI TSUKASA (2)· patent assignee history
2012–2016Based in Kanagawa, JP· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MITSUBISHI ELECTRIC CORP231991–2003
RENESAS TECH CORP72004–2010
RENESAS ELECTRONICS CORP32012–2016
MITSUI KATSUYOSHIself22012–2015
OISHI TSUKASA22012–2015
Locations
LocationPatentsSpan
Hyogo, JP301991–2005
Kanagawa, JP32012–2016
Tokyo, JP22000–2010