Inventor
DEPING HE
Inventor
US
Overview
Patents· 61 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing58%
G11CStatic stores34%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use8%
PatentTitleYear
12,578,891Assigning blocks of memory systems202612,578,865Memory block erase protocol202612,572,302Partitioned transferring for write booster202612,554,642Memory sub-system cache extension to page buffers of a memory array202612,525,315Efficient read disturb scanning202612,511,063Host recovery for a stuck condition202512,499,039Memory write performance techniques202512,487,883Critical data management within a memory system202512,474,865Write booster buffer and hibernate202512,443,264Shallow hibernate power state202512,430,246Out-of-order programming of first wordline in a physical unit of a memory device202512,399,827Techniques for enhanced system performance after retention loss202512,400,726Topology-based retirement in a memory system202512,366,959Data compression for mapping tables202512,362,030Techniques for retiring blocks of a memory system202512,321,631Suspension during a multi-plane write procedure202512,293,080Multiple memory block erase operation202512,292,831Enhanced data reliability in multi-level memory cells202512,210,448Virtual indexing in a memory device202512,182,027Cache block budgeting techniques202412,159,059Command sequence to support adaptive memory systems202412,124,322Access operation status signaling for memory systems202412,111,724Redundant array management techniques202412,099,734Memory block utilization in memory systems202412,079,481Memory block erase protocol202412,019,543Memory sub-system cache extension to page buffers of a memory array202412,002,531Techniques for retiring blocks of a memory system202411,983,112Techniques for enhanced system performance after retention loss202411,983,423Host recovery for a stuck condition202411,977,758Assigning blocks of memory systems202411,966,600Memory device with enhanced data reliability capabilities202411,960,398Enhanced data reliability in multi-level memory cells202411,942,174Topology-based retirement in a memory system202411,934,692Write booster buffer and hibernate202411,934,252Shallow hibernate power state202411,899,963Suspension during a multi-plane write procedure202411,886,266Dynamic power control202411,874,772Garbage collection adapted to host write activity202411,829,613Power behavior detection in a memory device202311,782,787Dynamic error control configuration for memory systems202311,726,863Memory data correction using multiple error control operations202311,720,253Access of a memory system based on fragmentation202311,720,261Transferring memory system data to a host system202311,721,398Techniques for determining memory cell read offsets202311,714,563Volatile register to detect power loss202311,709,617Multi-stage memory device performance notification202311,693,769Garbage collection adapted to memory device life expectancy202311,694,760Uncorrectable ECC202311,656,940Techniques for managing temporarily retired blocks of a memory system202311,561,892Garbage collection adapted to user device access202311,556,479Cache block budgeting techniques202311,550,711Dynamically adjusted garbage collection workload202311,494,095Power behavior detection in a memory device202211,380,419Methods to limit power during stress test and other limited supplies environment202211,314,427Memory device with enhanced data reliability capabilities202211,314,583Memory data correction using multiple error control operations202211,287,990Solid state storage device with quick boot from NAND media202211,288,149Flash memory block retirement policy202211,194,643Access operation status signaling for memory systems202111,188,461Garbage collection adapted to memory device life expectancy202111,158,387Techniques for determining memory cell read offsets2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to MICRON TECHNOLOGY INC (60)· patent assignee history
2021–2026Based in US· patent location history
2024Patents assigned to LODESTAR LICENSING GROUP LLC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 60 | 2021–2026 |
| LODESTAR LICENSING GROUP LLC | 1 | 2024 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 61 | 2021–2026 |