Inventor
Dinesh Jagannath Alladi
Inventor
San Diego, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Mprimary
H03MCoding42%
H03KPulse technique18%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses9%
H04BTransmission7%
G05FSystems for regulating electric or magnetic variables4%
G04FTime-interval measuring2%
G06FElectric digital data processing2%
G06GAnalogue computers2%
G11CStatic stores2%
H03FAmplifiers2%
PatentTitleYear
11,095,301Flash-successive approximation register (SAR) hybrid analog-to-digital converter (ADC)202110,651,864Time-interleaved charge sampler receiver202010,642,302Apparatus and method for generating reference DC voltage from bandgap-based voltage on data signal transmission line202010,594,308Digitally assisted control over comparator input common mode202010,461,762Successive approximation register analog-to-digital converter chopping201910,439,627Alias rejection through charge sharing201910,312,927Calibration for time-interleaved analog-to-digital converters and signal generators therefor201910,277,241Continuous-time analog-to-digital converter201910,243,578Continuous-time delta-sigma ADC with scalable sampling rates and excess loop delay compensation201910,044,365Time-to-digital converter (TDC)-based quantizer20189,998,138Time-multiplexed successive approximation register (SAR) analog-to-digital converter (ADC) circuits for multi-channel receivers20189,645,591'Charge sharing linear voltage regulator'20179,628,103'Multi-mode discrete-time delta-sigma modulator power optimization using split-integrator scheme'20179,473,165'Reducing signal dependence for CDAC reference voltage'20169,425,818'Noise shaping successive approximation register analog-to-digital converter'20169,411,987'Low noise and low power passive sampling network for a switched-capacitor ADC with a slow reference generator'20169,325,341'Excess loop delay compensation (ELC) for an analog to digital converter (ADC)'20169,306,553'Voltage level shifter with a low-latency voltage boost circuit'20169,300,316'Voltage doubling circuit for an analog to digital converter (ADC)'20169,197,198'Latch comparator circuits and methods'20158,994,568'Method and apparatus for closed loop control of supply and/or comparator common mode voltage in a successive approximation register analog to digital converter'20158,564,346'Non-overlapping clock generation'20138,169,243'Techniques for non-overlapping clock generation'20128,140,026'All-digital selectable duty cycle generation'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2021Patents assigned to QUALCOMM INC (24)· patent assignee history
2012–2013Patents assigned to ALLADI DINESH J (3)· patent assignee history
2012–2013Patents assigned to QUAN XIAOHONG (3)· patent assignee history
2012–2013Patents assigned to MATHE LENNART (2)· patent assignee history
2012–2013Patents assigned to SONG TONGYU (2)· patent assignee history
2012–2021Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 24 | 2012–2021 |
| ALLADI DINESH Jself | 3 | 2012–2013 |
| QUAN XIAOHONG | 3 | 2012–2013 |
| MATHE LENNART | 2 | 2012–2013 |
| SONG TONGYU | 2 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 24 | 2012–2021 |