Inventor
Suraj Mathew
Inventor
Boise, ID, US
Overview
Patents· 42 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Bprimary
H10BElectronic memory devices29%
H10DInorganic electric semiconductor devices26%
H01LSemiconductor devices16%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%
G11CStatic stores9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h108%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
PatentTitleYear
10,930,652Apparatuses including buried digit lines202110,854,611Memory cells and memory arrays202010,847,516Memory cells and memory arrays202010,546,862Integrated assemblies having spacers of low permittivity along digit-lines, and methods of forming integrated assemblies202010,361,204Memory cells and memory arrays201910,347,634Apparatuses including buried digit lines201910,319,724Memory cells and memory arrays201910,157,926Memory cells and memory arrays201810,079,235Memory cells and memory arrays201810,056,386Memory cells and memory arrays20189,947,666Semiconductor device structures including buried digit lines and related methods20189,852,953CMOS fabrication20179,214,394'CMOS fabrication'20159,059,030'Memory cells having capacitor dielectric directly against a transistor source/drain region'20159,054,216'Methods of forming a vertical transistor'20158,971,086'Capacitorless DRAM on bulk silicon'20158,859,367'Gate constructions of recessed access devices and methods of forming gate constructions of recessed access devices'20148,823,108'CMOS fabrication'20148,790,977'Methods of forming a vertical transistor, methods of forming memory cells, and methods of forming arrays of memory cells'20148,754,443'High density thyristor random access memory device and method'20148,722,480'Transistors having argon gate implants and methods of forming the same'20148,609,488'Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith'20138,466,517'Capacitorless DRAM on bulk silicon'20138,455,919'High density thyristor random access memory device and method'20138,450,175'Methods of forming a vertical transistor and at least a conductive line electrically coupled therewith'20138,378,430'Transistors having argon gate implants and methods of forming the same'20138,158,471'Capacitorless DRAM on bulk silicon'20128,067,286'Methods of forming recessed access devices associated with semiconductor constructions'20117,897,460'Methods of forming recessed access devices associated with semiconductor constructions'20117,858,458'CMOS fabrication'20107,829,399'Capacitorless DRAM on bulk silicon'20107,601,591'Method of manufacturing sidewall spacers on a memory device, and device comprising same'20097,538,389'Capacitorless DRAM on bulk silicon'20097,517,744'Capacitorless DRAM on bulk silicon'20097,462,534'Methods of forming memory circuitry'20087,459,742'Method of manufacturing sidewall spacers on a memory device, and device comprising same'20087,384,849'Methods of forming recessed access devices associated with semiconductor constructions'20087,341,906'Method of manufacturing sidewall spacers on a memory device, and device comprising same'20087,332,388'Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same'20087,005,342'Method to fabricate surface p-channel CMOS'20066,809,014'Method to fabricate surface p-channel CMOS'20046,797,596'Sacrificial deposition layer as screening material for implants into a wafer during the manufacture of a semiconductor device'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2021Patents assigned to MICRON TECHNOLOGY INC (42)· patent assignee history
2004–2021Based in Boise, ID, US· patent location history
2011–2015Patents assigned to MATHEW SURAJ J (5)· patent assignee history
2011–2013Patents assigned to TRIVEDI JIGISH D (3)· patent assignee history
2012–2018Patents assigned to MATHEW SURAJ (6)· patent assignee history
2013–2015Patents assigned to GUHA JAYDIP (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 42 | 2004–2021 |
| MATHEW SURAJself | 6 | 2012–2018 |
| MATHEW SURAJ Jself | 5 | 2011–2015 |
| GUHA JAYDIP | 3 | 2013–2015 |
| TRIVEDI JIGISH D | 3 | 2011–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 42 | 2004–2021 |