Inventor

Phillip J. Restle

Inventor

Katonah, NY, US

Overview

1997–2021

Patent span

Physics

Primary field (CPC G)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing47%

H03KPulse technique18%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%

G01RMeasuring electric variables8%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

H04LTransmission of digital information, e.g. telegraphic communication2%

A61BDiagnosis1%

G01DMeasuring not specially adapted for a specific variable1%

G05BControl or regulating systems in general1%

G11CStatic stores1%

PatentTitleYear

11,073,884On-chip supply noise voltage reduction or mitigation using local detection loops2021 11,036,276Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors2021 10,666,415Determining clock signal quality using a plurality of sensors2020 10,652,006Determining clock signal quality using a plurality of sensors2020 10,552,250Proactive voltage droop reduction and/or mitigation in a processor core2020 10,437,311Mitigation of on-chip supply voltage noise by monitoring slope of supply voltage based on time-based sensors2019 10,333,520On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core2019 10,261,561Mitigation of on-chip supply voltage based on local and non-local (neighboring) cores' supply voltage information and decision2019 10,171,081On-chip supply noise voltage reduction or mitigation using local detection loops in a processor core2019 10,145,892Increasing the resolution of on-chip measurement circuits2018 10,141,915Sequenced pulse-width adjustment in a resonant clocking circuit2018 9,800,232'Stitchable global clock for 3D chips'2017 9,705,479'Sequenced pulse-width adjustment in a resonant clocking circuit'2017 9,634,654'Sequenced pulse-width adjustment in a resonant clocking circuit'2017 9,618,966'Pulse-drive resonant clock with on-the-fly mode change'2017 9,612,612'Tunable sector buffer for wide bandwidth resonant global clock distribution'2017 9,612,614'Pulse-drive resonant clock with on-the-fly mode change'2017 9,575,119'Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping'2017 9,568,548'Measurement of signal delays in microprocessor integrated circuits with sub-picosecond accuracy using frequency stepping'2017 9,571,100'Clock buffers with pulse drive capability for power efficiency'2017 9,494,968'Clock skew analysis and optimization'2016 9,348,357'Stitchable global clock for 3D chips'2016 9,276,563'Clock buffers with pulse drive capability for power efficiency'2016 9,268,886'Setting switch size and transition pattern in a resonant clock distribution system'2016 9,251,913'Infrastructure for performance based chip-to-chip stacking'2016 9,231,603'Distributed phase detection for clock synchronization in multi-layer 3D stacks'2016 9,058,130'Tunable sector buffer for wide bandwidth resonant global clock distribution'2015 9,054,682'Wide bandwidth resonant global clock distribution'2015 8,887,118'Setting switch size and transition pattern in a resonant clock distribution system'2014 8,860,425'Defect detection on characteristically capacitive circuit nodes'2014 8,863,066'Wiring-optimal method to route high performance clock nets satisfying electrical and reliability constraints'2014 8,850,373'Setting switch size and transition pattern in a resonant clock distribution system'2014 8,775,996'Direct current circuit analysis based clock network design'2014 8,736,342'Changing resonant clock modes'2014 8,704,576'Variable resistance switch for wide bandwidth resonant global clock distribution'2014 8,677,305'Designing a robust power efficient clock distribution network'2014 8,525,569'Synchronizing global clocks in 3D stacks of integrated circuits by shorting the clock network'2013 8,516,426'Vertical power budgeting and shifting for three-dimensional integration'2013 7,962,887'Self-learning of the optimal power or performance operating point of a computer chip based on instantaneous feedback of present operating environment'2011 7,961,559'Duty cycle measurement circuit for measuring and maintaining balanced clock duty cycle'2011 7,941,689'Minimizing clock uncertainty on clock distribution networks using a multi-level de-skewing technique'2011 7,571,410'Resonant tree driven clock distribution grid'2009 7,456,671'Hierarchical scalable high resolution digital programmable delay circuit'2008 7,400,555'Built in self test circuit for measuring total timing uncertainty in a digital data path'2008 7,237,217'Resonant tree driven clock distribution grid'2007 7,117,455'System and method for derivative-free optimization of electrical circuits'2006 6,933,754'Clock gated power supply noise compensation'2005 6,531,759'Alpha particle shield for integrated circuit'2003 6,418,401'Efficient method for modeling three-dimensional interconnect structures for frequency-dependent crosstalk simulation'2002 6,342,823'System and method for reducing calculation complexity of lossy, frequency-dependent transmission-line computation'2002 6,311,313'X-Y grid tree clock distribution network with tunable tree and grid networks'2001 6,205,571'X-Y grid tree tuning method'2001 6,006,025'Method of clock routing for semiconductor chips'1999 5,610,528'Capacitive bend sensor'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2021Patents assigned to IBM (54)· patent assignee history

1997–2021Based in Katonah, NY, US· patent location history

2013–2016Patents assigned to KURSUN EREN (2)· patent assignee history

2013–2014Patents assigned to PANG LIANG-TECK (2)· patent assignee history

2013Patents assigned to RESTLE PHILLIP J (2)· patent assignee history

2014–2016Patents assigned to RESTLE PHILLIP JOHN (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	54	1997–2021
RESTLE PHILLIP JOHNself	3	2014–2016
KURSUN EREN	2	2013–2016
PANG LIANG-TECK	2	2013–2014
RESTLE PHILLIP Jself	2	2013

Locations

Location	Patents	Span
Katonah, New York, US	54	1997–2021