Inventor
Yusuke Matsunaga
Inventor
Amherst, NY, US
Overview
Patents· 14 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
F28FDetails of heat-exchange and heat-transfer apparatus, of general application15%
Y10TTechnical subjects covered by former us classification12%
F28DHeat-exchange apparatus, not provided for in another subclass, in which the heat-exchange media do not come into direct contact8%
G01RMeasuring electric variables8%
G11CStatic stores8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
PatentTitleYear
10,520,549Semiconductor device, diagnostic test, and diagnostic test circuit20199,810,738'Semiconductor device, diagnostic test, and diagnostic test circuit'20177,490,271'Semiconductor device mounting chip having tracing function'20097,260,893'Method of attaching a transmission oil cooler to an aluminum tank'20077,147,040'Heat exchanger with tank utilizing integral positioning guides'20067,146,543'Semiconductor device mounting chip having tracing function'20067,059,050'One piece integral reinforcement with angled end caps to facilitate assembly to core'20067,007,743'Header tank with integral mounting flange'20066,625,799'Technology mapping method and storage medium'20035,909,374'System and method for verifying logic circuit based on signal line set affecting internal signal'19995,734,917'System for producing combination circuit to satisfy prescribed delay time by deleting selected path gate and allowing to perform the permissible function for initial circuit'19985,535,132'Variable sequence determining method for a dichotomy determination graph'19965,490,268'Method for changing an arrangement of an initial combinational circuit to satisfy prescribed delay time by computing permissible functions of output gates and remaining gates'19965,461,574'Method of expressing a logic circuit'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2003Patents assigned to FUJITSU LTD (6)· patent assignee history
1995–1998Based in Yokohama, JP· patent location history
1999–2017Based in Kawasaki, JP· patent location history
2006–2007Patents assigned to DELPHI TECH INC (4)· patent assignee history
2006–2009Patents assigned to RENESAS TECH CORP (2)· patent assignee history
2006–2007Based in Amherst, NY, US· patent location history
2006–2009Based in Hyogo, JP· patent location history
2017–2019Patents assigned to RENESAS ELECTRONICS CORP (2)· patent assignee history
2019Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJITSU LTD | 6 | 1995–2003 |
| DELPHI TECH INC | 4 | 2006–2007 |
| RENESAS ELECTRONICS CORP | 2 | 2017–2019 |
| RENESAS TECH CORP | 2 | 2006–2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Amherst, New York, US | 4 | 2006–2007 |
| Kawasaki, JP | 3 | 1999–2017 |
| Yokohama, JP | 3 | 1995–1998 |
| Hyogo, JP | 2 | 2006–2009 |
| Tokyo, JP | 1 | 2019 |