Inventor
Darryl J. Becker
Inventor
Rochester, MN, US
Overview
Patents· 106 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing24%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H05KPrinted circuits9%
G11CStatic stores5%
H04LTransmission of digital information, e.g. telegraphic communication4%
H01LSemiconductor devices3%
Y10TTechnical subjects covered by former us classification3%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy3%
G01RMeasuring electric variables3%
G06VImage or video recognition or understanding3%
PatentTitleYear
10,955,568X-ray sensitive device to detect an inspection202110,916,493Direct current blocking capacitors202110,834,830Creating in-via routing with a light pipe202010,834,828Creating inductors, resistors, capacitors and other structures in printed circuit board vias with light pipe technology202010,712,664Forming conductive vias using a light guide202010,715,337Secure crypto module including conductor on glass security layer202010,657,290Authentication using optically sensed relative position202010,622,316Security arrangement for integrated circuits using microcapsules in dielectric layer202010,559,902Electrical connection management using a card202010,548,216Employing conductive track writing in a tamper-respondent system202010,547,640Secure crypto module including electrical shorting security layers202010,499,744Removable back rest201910,481,496Forming conductive vias using a light guide201910,433,431Implementing customized PCB via creation through use of magnetic pads201910,342,142Implementing customized PCB via creation through use of magnetic pads201910,318,462Secure crypto module including optical glass security layer201910,303,639Secure crypto module including optical glass security layer201910,169,623Security apparatus for computing systems201910,171,498Secure crypto module including electrical shorting security layers201910,157,527Embossed printed circuit board for intrusion detection201810,117,517Removable back rest201810,055,380Dynamic clock lane assignment for increased performance and security201810,055,612Authentication using optically sensed relative position201810,025,751Dynamic clock lane assignment for increased performance and security20189,965,438Dynamic clock lane assignment for increased performance and security20189,887,840'Scrambling bit transmissions'20189,887,847'Secure crypto module including conductor on glass security layer'20189,739,825'Residual material detection in backdrilled stubs'20179,680,477'Printed circuit board security using embedded photodetector circuit'20179,665,797'Environmental-based location monitoring'20179,665,736'Authentication using optically sensed relative position'20179,652,636'Verifying motion data for accessing hardware elements'20179,612,988'Donor cores to improve integrated circuit yield'20179,569,644'Verifying motion data for accessing hardware elements'20179,568,940'Multiple active vertically aligned cores for three-dimensional chip stack'20179,536,176'Environmental-based location monitoring'20179,515,401'Elastomeric electrical connector structure joining two hardware planes at right angles to each other'20169,488,690'Residual material detection in backdrilled stubs'20169,438,606'Environmental-based location monitoring'20169,341,670'Residual material detection in backdrilled stubs'20169,310,827'Multiple active vertically aligned cores for three-dimensional chip stack'20169,312,199'Intelligent chip placement within a three-dimensional chip stack'20169,281,261'Intelligent chip placement within a three-dimensional chip stack'20169,003,559'Continuity check monitoring for microchip exploitation detection'20158,823,090'Field-effect transistor and method of creating same'20148,796,578'Implementing selective rework for chip stacks and silicon carrier assemblies'20148,519,304'Implementing selective rework for chip stacks and silicon carrier assemblies'20138,466,024'Power domain controller with gated through silicon via having FET with horizontal channel'20138,332,659'Signal quality monitoring to defeat microchip exploitation'20128,214,657'Resistance sensing for defeating microchip exploitation'20128,172,140'Doped implant monitoring for microchip tamper detection'20128,174,103'Enhanced architectural interconnect options enabled with flipped die on a multi-chip package'20128,108,647'Digital data architecture employing redundant links in a daisy chain of component modules'20128,079,134'Method of enhancing on-chip inductance structure utilizing silicon through via technology'20117,952,478'Capacitance-based microchip exploitation detection'20117,954,081'Implementing enhanced wiring capability for electronic laminate packages'20117,945,883'Apparatus, and computer program for implementing vertically coupled noise control through a mesh plane in an electronic package design'20117,884,625'Capacitance structures for defeating microchip tampering'20117,882,479'Method and apparatus for implementing redundant memory access using multiple controllers on the same bank of memory'20117,852,103'Implementing at-speed Wafer Final Test (WFT) with complete chip coverage'20107,844,769'Computer system having an apportionable data bus and daisy chained memory chips'20107,838,336'Method and structure for dispensing chip underfill through an opening in the chip'20107,810,065'System and method for implementing optimized creation of openings for de-gassing in an electronic package'20107,791,978'Design structure of implementing power savings during addressing of DRAM architectures'20107,725,762'Implementing redundant memory access using multiple controllers on the same bank of memory'20107,701,244'False connection for defeating microchip exploitation'20107,675,164'Method and structure for connecting, stacking, and cooling chips on a flexible carrier'20107,673,093'Computer system having daisy chained memory chips'20107,667,487'Techniques for providing switchable decoupling capacitors for an integrated circuit'20107,660,940'Carrier having daisy chain of self timed memory chips'20107,660,942'Daisy chainable self timed memory chip'20107,650,455'Spider web interconnect topology utilizing multiple port connection'20107,627,711'Memory controller for daisy chained memory chips'20097,620,763'Memory chip having an apportionable data bus'20097,617,350'Carrier having daisy chained memory chips'20097,577,811'Memory controller for daisy chained self timed memory chips'20097,553,696'Method for implementing component placement suspended within grid array packages for enhanced electrical performance'20097,545,664'Memory system having self timed daisy chained memory chips'20097,546,410'Self timed memory chip having an apportionable data bus'20097,492,662'Structure and method of implementing power savings during addressing of DRAM architectures'20097,490,186'Memory system having an apportionable data bus and daisy chained memory chips'20097,480,201'Daisy chainable memory chip'20097,477,568'Using common mode differential data signals of DDR2 SDRAM for control signal transmission'20097,472,360'Method for implementing enhanced wiring capability for electronic laminate packages'20087,472,368'Method for implementing vertically coupled noise control through a mesh plane in an electronic package design'20087,402,912'Method and power control structure for managing plurality of voltage islands'20087,362,651'Using common mode differential data signals of DDR2 SDRAM for control signal transmission'20087,345,900'Daisy chained memory system'20087,345,901'Computer system having daisy chained self timed memory chips'20087,342,816'Daisy chainable memory chip'20087,272,809'Method, apparatus and computer program product for implementing enhanced high frequency return current paths utilizing decoupling capacitors in a package design'20077,202,685'Embedded probe-enabling socket with integral probe structures'20077,088,199'Method and stiffener-embedded waveguide structure for implementing enhanced data transfer'20067,088,200'Method and structure to control common mode impedance in fan-out regions'20067,074,050'Socket assembly with incorporated memory structure'20067,055,119'Customized mesh plane, method and computer program product for creating customized mesh planes within electronic packages'20067,050,871'Method and apparatus for implementing silicon wafer chip carrier passive devices'20067,036,710'Method and structures for implementing impedance-controlled coupled noise suppressor for differential interface solder column array'20067,036,709'Method and structure for implementing column attach coupled noise suppressor'20066,998,852'Method and apparatus for implementing direct attenuation measurement through embedded structure excitation'20066,993,739'Method, structure, and computer program product for implementing high frequency return current paths within electronic packages'20066,261,404'Heat dissipation apparatus and method for attaching a heat dissipation apparatus to an electronic device'20015,905,636'Heat dissipation apparatus and method for attaching a heat dissipation apparatus to an electronic device'19995,745,344'Heat dissipation apparatus and method for attaching a heat dissipation apparatus to an electronic device'19985,419,483'Method and apparatus for manufacturing a printed circuit card and connector assembly'19955,318,212'Method and apparatus for manufacturing a printed circuit card and connector assembly'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2021Patents assigned to IBM (104)· patent assignee history
1994–2021Based in Rochester, MN, US· patent location history
2012–2015Patents assigned to BARTLEY GERALD K (6)· patent assignee history
2012–2015Patents assigned to BECKER DARRYL J (6)· patent assignee history
2012–2015Patents assigned to GERMANN PHILIP R (6)· patent assignee history
2012–2015Patents assigned to MAKI ANDREW B (6)· patent assignee history
2018–2019Based in Cost, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 104 | 1994–2021 |
| BARTLEY GERALD K | 6 | 2012–2015 |
| BECKER DARRYL Jself | 6 | 2012–2015 |
| GERMANN PHILIP R | 6 | 2012–2015 |
| MAKI ANDREW B | 6 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Rochester, Minnesota, US | 104 | 1994–2021 |
| Cost, Texas, US | 2 | 2018–2019 |