Inventor
Sujeet Ayyapureddi
Inventor
Boise, ID, US
Overview
Patents· 28 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores58%
G06FElectric digital data processing16%
H03KPulse technique11%
G01KMeasuring temperature8%
H01LSemiconductor devices3%
H03MCoding3%
H10BElectronic memory devices3%
PatentTitleYear
10,984,886Reduced footprint fuse circuit202110,964,378Apparatus and method including analog accumulator for determining row access rate and target row address used for refresh operation202110,949,284Techniques using nonvolatile memory and volatile memory202110,867,692Apparatuses and methods for latching redundancy repair addresses at a memory202010,600,498Reduced footprint fuse circuit202010,381,103Apparatuses and methods for latching redundancy repair addresses to avoid address bits overwritten at a repair block20199,810,589'System and method for automatically calibrating a temperature sensor'20179,740,269'Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination'20179,665,462'Apparatuses and methods for arbitrating a shared terminal for calibration of an impedance termination'20179,570,201'Repair of memory devices using volatile and non-volatile memory'20179,508,409'Apparatuses and methods for implementing masked write commands'20169,405,721'Apparatuses and methods for performing a databus inversion operation'20169,349,491'Repair of memory devices using volatile and non-volatile memory'20169,213,553'System and method for configuring drivers'20158,862,421'System and method for automatically calibrating a temperature sensor'20148,566,846'System and method for configuring drivers'20138,243,544'Reduction of fusible links and associated circuitry on memory dies'20128,190,849'Sharing physical memory locations in memory devices'20127,952,952'Reduction of fusible links and associated circuitry on memory dies'20117,864,577'Sharing physical memory locations in memory devices'20117,809,519'System and method for automatically calibrating a temperature sensor'20107,804,324'Dynamically adjusting operation of a circuit within a semiconductor device'20107,573,288'Dynamically adjusting operation of a circuit within a semiconductor device'20097,388,801'Reduction of fusible links and associated circuitry on memory dies'20087,102,956'Reduction of fusible links and associated circuitry on memory dies'20067,102,957'Reduction of fusible links and associated circuitry on memory dies'20067,102,955'Reduction of fusible links and associated circuitry on memory dies'20067,046,560'Reduction of fusible links and associated circuitry on memory dies'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2021Patents assigned to MICRON TECHNOLOGY INC (28)· patent assignee history
2006–2021Based in Boise, ID, US· patent location history
2012–2014Patents assigned to AYYAPUREDDI SUJEET (3)· patent assignee history
2012Patents assigned to AYYAPUREDDI SUJEET V (1)· patent assignee history
2012Patents assigned to SEERAM VASU (1)· patent assignee history
2014Patents assigned to ROTH BRANDON (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 28 | 2006–2021 |
| AYYAPUREDDI SUJEETself | 3 | 2012–2014 |
| AYYAPUREDDI SUJEET Vself | 1 | 2012 |
| ROTH BRANDON | 1 | 2014 |
| SEERAM VASU | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Boise, ID, US | 28 | 2006–2021 |