Inventor
Gustavo E. Tellez
Inventor
Essex Junction, VT, US
Overview
Patents· 44 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing66%
Y02PClimate change mitigation technologies in the production or processing of goods7%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
G06TImage data processing or generation, in general5%
H10DInorganic electric semiconductor devices5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
G01RMeasuring electric variables2%
G11CStatic stores2%
H03KPulse technique2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
11,120,192White space insertion for enhanced routability202111,087,062Dynamic SADP region generation202111,074,379Multi-cycle latch tree synthesis202110,831,972Capacity model for global routing202010,796,064Autonomous placement to satisfy self-aligned double patterning constraints202010,747,935Identification of hotspots in congestion analysis during physical design of integrated circuit202010,726,187Self-aligned double patterning-aware routing in chip manufacturing202010,719,656Triple and quad coloring of shape layouts202010,606,978Triple and quad coloring of shape layouts202010,606,976Engineering change order aware global routing202010,503,841Integrated circuit buffering solutions considering sink delays201910,496,764Integrated circuit buffering solutions considering sink delays201910,372,836Integrated circuit buffering solutions considering sink delays201910,372,837Integrated circuit buffering solutions considering sink delays201910,346,558Integrated circuit buffering solutions considering sink delays201910,229,239Capacity model for global routing201910,223,496Triple and quad coloring shape layouts201910,216,882Critical path straightening system based on free-space aware and timing driven incremental placement20199,245,076'Orthogonal circuit element routing'20169,158,885'Reducing color conflicts in triple patterning lithography'20158,938,702'Timing driven routing for noise reduction in integrated circuit design'20158,631,375'Via selection in integrated circuit design'20148,448,110'Method to reduce delay variation by sensitivity cancellation'20138,347,257'Detailed routability by cell placement'20138,230,378'Method for IC wiring yield optimization, including wire widening during and after routing'20127,961,932'Method and apparatus for manufacturing diamond shaped chips'20117,895,545'Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning'20117,725,864'Systematic yield in semiconductor manufacture'20107,721,240'Systematic yield in semiconductor manufacture'20107,657,859'Method for IC wiring yield optimization, including wire widening during and after routing'20107,337,415'Systematic yield in semiconductor manufacture'20087,289,659'Method and apparatus for manufacturing diamond shaped chips'20077,117,456'Circuit area minimization using scaling'20067,076,749'Method and system for improving integrated circuit manufacturing productivity'20067,062,729'Method and system for obtaining a feasible integer solution from a half-integer solution in hierarchical circuit layout optimization'20066,993,692'Method, system and apparatus for aggregating failures across multiple memories and applying a common defect repair solution to all of the multiple memories'20066,986,109'Practical method for hierarchical-preserving layout optimization of integrated circuit layout'20066,941,528'Use of a layout-optimization tool to increase the yield and reliability of VLSI designs'20056,904,575'Method for improving chip yields in the presence of via flaring'20056,738,954'Method for prediction random defect yields of integrated circuits with accuracy and computation time controls'20046,305,004'Method for improving wiring related yield and capacitance properties of integrated circuits by maze-routing'20016,301,690'Method to improve integrated circuit defect limited yield'20016,247,853'Incremental method for critical area and critical region computation of via blocks'20016,189,132'Design rule correction system and method'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2021Patents assigned to IBM (44)· patent assignee history
2001Based in Cornwall-on-Hudson, NY, US· patent location history
2004–2021Based in Essex Junction, VT, US· patent location history
2008Based in Essex, VT, US· patent location history
2012–2014Patents assigned to TELLEZ GUSTAVO E (4)· patent assignee history
2013–2014Patents assigned to HUBER ANDREW D (2)· patent assignee history
2013Patents assigned to ALPERT CHARLES J (1)· patent assignee history
2014Patents assigned to ARELT ROBERT R (1)· patent assignee history
2019–2021Based in Hyde Park, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 44 | 2001–2021 |
| TELLEZ GUSTAVO Eself | 4 | 2012–2014 |
| HUBER ANDREW D | 2 | 2013–2014 |
| ALPERT CHARLES J | 1 | 2013 |
| ARELT ROBERT R | 1 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 37 | 2004–2021 |
| Cornwall-on-Hudson, New York, US | 4 | 2001 |
| Hyde Park, New York, US | 2 | 2019–2021 |
| Essex, VT, US | 1 | 2008 |