Inventor
Kamran Zarrineh
Inventor
Billerica, MA, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores38%
G06FElectric digital data processing19%
G01RMeasuring electric variables15%
G01KMeasuring temperature8%
G05FSystems for regulating electric or magnetic variables8%
H03KPulse technique4%
H03MCoding4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
PatentTitleYear
10,310,015Method and apparatus for providing clock signals for a scan chain20197,293,199'Method and apparatus for testing memories with different read/write protocols using the same programmable memory bist controller'20077,260,759'Method and apparatus for an efficient memory built-in self test architecture for high performance microprocessors'20077,206,979'Method and apparatus for at-speed diagnostics of embedded memories'20077,178,076'Architecture of an efficient at-speed programmable memory built-in self test'20077,168,005'Programable multi-port memory BIST with compact microcode'20077,032,144'Method and apparatus for testing multi-port memories'20066,937,958'Controller for monitoring temperature'20056,893,154'Integrated temperature sensor'20056,874,111'System initialization of microcode-based memory built-in self-test'20056,813,201'Automatic generation and validation of memory test models'20046,809,557'Increasing power supply noise rejection using linear voltage regulators in an on-chip temperature sensor'20046,806,698'Quantifying a difference between nodal voltages'20046,700,946'System and method for automatic generation of an at-speed counter'20046,681,350'Method and apparatus for testing memory cells for data retention faults'20046,651,201'Programmable memory built-in self-test combining microcode and finite state machine self-test'20036,605,988'Low voltage temperature-independent and temperature-dependent voltage generator'20036,557,127'Method and apparatus for testing multi-port memories'20035,691,990'Hybrid partial scan method'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2005Patents assigned to IBM (3)· patent assignee history
2003–2007Patents assigned to SUN MICROSYSTEMS INC (11)· patent assignee history
2003–2007Patents assigned to CADENCE DESIGN SYSTEMS INC (4)· patent assignee history
2003–2007Based in Billerica, MA, US· patent location history
2003–2007Based in Vestal, NY, US· patent location history
2003–2006Based in Vescal, NY, US· patent location history
2004–2005Based in Nashua, NH, US· patent location history
2019Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history
2019Based in Topsfield, MA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SUN MICROSYSTEMS INC | 11 | 2003–2007 |
| CADENCE DESIGN SYSTEMS INC | 4 | 2003–2007 |
| IBM | 3 | 1997–2005 |
| ADVANCED MICRO DEVICES INC | 1 | 2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Billerica, Massachusetts, US | 8 | 2003–2007 |
| Vestal, New York, US | 4 | 2003–2007 |
| Nashua, NH, US | 3 | 2004–2005 |
| Vescal, New York, US | 2 | 2003–2006 |
| Topsfield, Massachusetts, US | 1 | 2019 |