Inventor
Dustin P. Wood
Inventor
Chandler, AZ, US
Overview
Patents· 29 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1038%
H05KPrinted circuits19%
H01GCapacitors14%
Y10TTechnical subjects covered by former us classification9%
H10DInorganic electric semiconductor devices5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
B82YSpecific uses or applications of nanostructures4%
G06FElectric digital data processing3%
H01LSemiconductor devices3%
PatentTitleYear
10,522,455Integrated circuit package substrate201910,242,942Integrated circuit package substrate20197,755,165'iTFC with optimized C(T)'20107,687,905'Integrated circuit packages, systems, and methods'20107,667,320'Integrated circuit package with improved power signal connection'20107,656,644'iTFC with optimized C(T)'20107,524,754'Interconnect shunt used for current distribution and reliability redundancy'20097,495,336'Array capacitors for broadband decoupling applications'20097,463,492'Array capacitors with voids to enable a full-grid socket'20087,375,412'iTFC with optimized C(T)'20087,365,428'Array capacitor with resistive structure'20087,355,836'Array capacitor for decoupling multiple voltage rails'20087,348,214'Integrated circuit package with improved power signal connection'20087,339,263'Integrated circuit packages, systems, and methods'20087,321,172'Selective plating of package terminals'20087,265,995'Array capacitors with voids to enable a full-grid socket'20077,243,423'Chip package with degassing holes'20077,208,830'Interconnect shunt used for current distribution and reliability redundancy'20077,186,645'Selective plating of package terminals'20077,183,644'Integrated circuit package with improved power signal connection'20077,173,804'Array capacitor with IC contacts and applications'20077,152,313'Package substrate for integrated circuit and method of making the substrate'20066,979,891'Integrated circuit packaging architecture'20056,867,491'Metal core integrated circuit package with electrically isolated regions and associated methods'20056,831,233'Chip package with degassing holes'20046,819,543'Multilayer capacitor with multiple plates per layer'20046,501,166'Stitched plane structure and process for package power delivery and dual referenced stripline I/O performance'20026,429,051'Stitched plane structure for package power delivery and dual referenced stripline I/O performance'20026,225,687'Chip package with degassing holes'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2019Patents assigned to INTEL CORP (29)· patent assignee history
2001–2007Based in Phoenix, AZ, US· patent location history
2002–2019Based in Chandler, AZ, US· patent location history
2019Patents assigned to MALLIK DEBENDRA (1)· patent assignee history
2019Patents assigned to MANUSHAROW MATHEW J (1)· patent assignee history
2019Patents assigned to WOOD DUSTIN P (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 29 | 2001–2019 |
| MALLIK DEBENDRA | 1 | 2019 |
| MANUSHAROW MATHEW J | 1 | 2019 |
| WOOD DUSTIN Pself | 1 | 2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| Chandler, AZ, US | 26 | 2002–2019 |
| Phoenix, AZ, US | 3 | 2001–2007 |