LexDanaLexDanabeta
Inventor

Andreas Kuehlmann

Inventor
Berkeley, CA, US

Overview

23→
Patents
1997–2020
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing96%
G01RMeasuring electric variables4%
PatentTitleYear
10,713,069Software and hardware emulation system20209,836,390Static analysis of computer code to determine impact of change to a code component upon a dependent code component20179,612,943'Prioritization of tests of computer program code'20179,317,399'Policy evaluation based upon dynamic observation, static analysis and code change history'20169,032,376'Static analysis of computer code to determine impact of change to a code component upon a dependent code component'20158,862,439'General numeric backtracking algorithm for solving satifiability problems to verify functionality of circuits and software'20148,656,330'Apparatus with general numeric backtracking algorithm for solving satisfiability problems to verify functionality of circuits and software'20148,589,845'Optimizing integrated circuit design through use of sequential timing information'20138,418,101'Temporal decomposition for design and verification'20138,413,090'Temporal decomposition for design and verification'20138,307,316'Reducing critical cycle delay in an integrated circuit design through use of sequential slack'20128,020,125'System, methods and apparatus for generation of simulation stimulus'20117,913,210'Reducing critical cycle delay in an integrated circuit design through use of sequential slack'20117,900,173'Temporal decomposition for design and verification'20117,743,354'Optimizing integrated circuit design through use of sequential timing information'20107,624,364'Data path and placement optimization in an integrated circuit through use of sequential timing information'20097,596,770'Temporal decomposition for design and verification'20097,559,040'Optimization of combinational logic synthesis through clock latency scheduling'20097,296,246'Multi-domain clock skew scheduling'20076,698,003'Framework for multiple-engine based verification tools for integrated circuits'20046,473,884'Method and system for equivalence-checking combinatorial circuits using interative binary-decision-diagram sweeping and structural satisfiability analysis'20026,035,107'Method for performing functional comparison of combinational circuits'20005,629,858'CMOS transistor network to gate level model extractor for simulation, verification and test generation'1997

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1997–2004Patents assigned to IBM (4)· patent assignee history
1997–2000Based in Poughkeepsie, NY, US· patent location history
2002Based in Austin, TX, US· patent location history
2004–2020Based in Berkeley, CA, US· patent location history
2007–2014Patents assigned to CADENCE DESIGN SYSTEMS INC (12)· patent assignee history
2012–2014Patents assigned to KUEHLMANN ANDREAS (6)· patent assignee history
2012–2013Patents assigned to ALBRECHT CHRISTOPH (2)· patent assignee history
2014Based in Kensington, CA, US· patent location history
2015–2020Patents assigned to SYNOPSYS INC (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
CADENCE DESIGN SYSTEMS INC122007–2014
KUEHLMANN ANDREASself62012–2014
SYNOPSYS INC52015–2020
IBM41997–2004
ALBRECHT CHRISTOPH22012–2013
Locations
LocationPatentsSpan
Berkeley, California, US182004–2020
Kensington, California, US22014
Poughkeepsie, New York, US21997–2000
Austin, Texas, US12002