Inventor
Kenneth D. Klapproth
Inventor
Austin, TX, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
G11CStatic stores6%
G01RMeasuring electric variables3%
H03KPulse technique3%
PatentTitleYear
10,956,637Placement-driven generation of error detecting structures in integrated circuits202110,915,461Multilevel cache eviction management202110,884,890Accuracy sensitive performance counters202110,831,661Coherent cache with simultaneous data requests in same addressable index202010,802,966Simultaneous, non-atomic request processing within an SMP environment broadcast scope for multiply-requested data elements using real-time parallelization202010,540,251Accuracy sensitive performance counters202010,489,292Ownership tracking updates across multiple simultaneous operations201910,482,015Ownership tracking updates across multiple simultaneous operations201910,379,776Operation interlocking in an address-sliced cache system201910,325,049Placement-driven generation of error detecting structures in integrated circuits20199,734,110'Dynamic synchronous to asynchronous frequency transitions in high-performance symmetric multiprocessing'20179,003,127'Storing data in a system memory for a subsequent cache flush'20158,990,507'Storing data in a system memory for a subsequent cache flush'20158,930,616'System refresh in cache memory'20158,706,972'Dynamic mode transitions for cache instructions'20148,639,887'Dynamically altering a pipeline controller mode based on resource availability'20148,635,409'Dynamic mode transitions for cache instructions'20148,478,920'Controlling data stream interruptions on a shared interface'20138,458,405'Cache bank modeling with variable access and busy times'20138,291,157'Concurrent refresh in cache memory'20127,529,799'Method and apparatus for transaction tag assignment and maintenance in a distributed symmetric multiprocessor system'20096,904,585'Method for identification and removal of non-timing critical wire routes from congestion region'20056,816,826'Fully exhibiting asynchronous behavior in a logic network simulation'20046,580,288'Multi-property microprocessor with no additional logic overhead to shared pins'20036,510,471'Method for choosing device among plurality of devices based on coherncy status of device\'s data and if device supports higher-performance transactions'20036,484,220'Transfer of data between processors in a multi-processor system'20026,134,684'Method and system for error detection in test units utilizing pseudo-random data'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2021Patents assigned to IBM (27)· patent assignee history
2000–2021Based in Austin, TX, US· patent location history
2012–2015Patents assigned to KLAPPROTH KENNETH D (6)· patent assignee history
2012–2015Patents assigned to BRONSON TIMOTHY C (3)· patent assignee history
2012–2015Patents assigned to HUYNH HIEU T (3)· patent assignee history
2013–2014Patents assigned to SONNELITTER III ROBERT J (3)· patent assignee history
2019–2021Based in Travis, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 27 | 2000–2021 |
| KLAPPROTH KENNETH Dself | 6 | 2012–2015 |
| BRONSON TIMOTHY C | 3 | 2012–2015 |
| HUYNH HIEU T | 3 | 2012–2015 |
| SONNELITTER III ROBERT J | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 22 | 2000–2021 |
| Travis, Texas, US | 5 | 2019–2021 |