Inventor
Srinivas Perisetty
Inventor
Santa Clara, CA, US
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Kprimary
H03KPulse technique25%
G11CStatic stores22%
H10DInorganic electric semiconductor devices16%
G06FElectric digital data processing8%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems8%
H01LSemiconductor devices6%
G05FSystems for regulating electric or magnetic variables4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G01RMeasuring electric variables2%
H02HEmergency protective circuit arrangements2%
PatentTitleYear
10,200,037Apparatus and methods for on-die temperature sensing to improve FPGA performance20199,735,779'Apparatus and methods for on-die temperature sensing to improve FPGA performance'20179,496,268'Integrated circuits with asymmetric and stacked transistors'20168,750,026'Integrated circuits with asymmetric and stacked transistors'20148,732,635'Apparatus and methods for power management in integrated circuits'20148,711,614'Memory elements with increased write margin and soft error upset immunity'20148,618,786'Self-biased voltage regulation circuitry for memory'20138,482,963'Integrated circuits with asymmetric and stacked transistors'20138,369,175'Memory elements with voltage overstress protection'20138,279,660'Static random-access memory with boosted voltages'20128,099,704'Performance improvements in an integrated circuit by selectively applying forward bias voltages'20127,990,664'Electrostatic discharge protection in a field programmable gate array'20117,978,450'Electrostatic discharge protection circuitry'20117,957,177'Static random-access memory with boosted voltages'20117,920,410'Memory elements with increased write margin and soft error upset immunity'20117,863,968'Variable-output current-load-independent negative-voltage regulator'20117,782,581'Method and apparatus for providing electrostatic discharge protection for a polysilicon fuse'20107,675,317'Integrated circuits with adjustable body bias and power supply circuitry'20107,639,067'Integrated circuit voltage regulator'20097,639,041'Hotsocket-compatible body bias circuitry with power-up current reduction capabilities'20097,629,831'Booster circuit with capacitor protection circuitry'20097,592,832'Adjustable transistor body bias circuitry'20097,571,413'Testing circuitry for programmable logic devices with selectable power supply voltages'20097,514,953'Adjustable transistor body bias generation circuitry with latch-up prevention'20097,511,932'ESD protection structure'20097,501,849'Latch-up prevention circuitry for integrated circuits with transistor body biasing'20097,495,471'Adjustable transistor body bias circuitry'20097,405,589'Apparatus and methods for power management in integrated circuits'20087,355,437'Latch-up prevention circuitry for integrated circuits with transistor body biasing'20087,330,049'Adjustable transistor body bias generation circuitry with latch-up prevention'20087,296,196'Redundant column read in a memory array'20076,879,535'Approach for zero dummy byte flash memory read operation'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2007Patents assigned to ATMEL CORP (2)· patent assignee history
2005Based in San Jose, CA, US· patent location history
2007–2019Based in Santa Clara, CA, US· patent location history
2008–2019Patents assigned to ALTERA CORP (30)· patent assignee history
2012–2017Patents assigned to PERISETTY SRINIVAS (8)· patent assignee history
2013–2014Patents assigned to LEE ANDY L (4)· patent assignee history
2013–2014Patents assigned to RAHIM IRFAN (3)· patent assignee history
2013Based in Hyderabad, IN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ALTERA CORP | 30 | 2008–2019 |
| PERISETTY SRINIVASself | 8 | 2012–2017 |
| LEE ANDY L | 4 | 2013–2014 |
| RAHIM IRFAN | 3 | 2013–2014 |
| ATMEL CORP | 2 | 2005–2007 |
Locations
| Location | Patents | Span |
|---|---|---|
| Santa Clara, California, US | 30 | 2007–2019 |
| Hyderabad, IN | 1 | 2013 |
| San Jose, California, US | 1 | 2005 |