Inventor
Jeremy Isaac Nathaniel Werner
Inventor
San Jose, CA, US
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing48%
G11CStatic stores18%
H04LTransmission of digital information, e.g. telegraphic communication14%
H03MCoding9%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G11BInformation storage based on relative movement between record carrier and transducer2%
H05KPrinted circuits2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y02PClimate change mitigation technologies in the production or processing of goods2%
PatentTitleYear
10,904,011Configuration updates for access-restricted hosts202110,891,569Dynamic task discovery for workflow tasks202110,803,970Solid-state disk manufacturing self test202010,467,093Non-volatile memory program failure recovery via redundant arrays201910,073,734Flash memory read error recovery with soft-decision decode20189,614,674'Virtual bands concentration for self encrypting drives'20179,569,320'Non-volatile memory program failure recovery via redundant arrays'20179,443,616'Bad memory unit detection in a solid state drive'20169,405,624'On-die error detection and correction during multi-step programming'20169,183,140'Higher-level redundancy information computation'20159,135,112'Policy for read operations addressing on-the-fly decoding failure in non-volatile memory'20159,117,086'Virtual bands concentration for self encrypting drives'20159,105,305'Dynamic higher-level redundancy mode management with independent silicon elements'20159,021,332'Flash memory read error recovery with soft-decision decode'20159,007,842'Retention detection and/or channel tracking policy in a flash memory based storage system'20158,996,961'Error correction code rate management for nonvolatile memory'20158,656,101'Higher-level redundancy information computation'20148,356,361'Secure co-processing memory controller integrated into an embedded memory subsystem'20138,261,091'Solid-state memory-based generation and handling of security authentication tokens'20128,190,919'Multiple stakeholder secure memory partitioning and access control'20128,190,908'Secure data verification via biometric input'20128,190,885'Non-volatile memory sub-system integrated with security for storing near field transactions'20128,117,445'Near field communication, security and non-volatile memory integrated sub-system for embedded portable applications'20128,080,874'Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween'20117,836,269'Systems and methods for access violation management of secured memory'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2013Patents assigned to SPANSION LLC (7)· patent assignee history
2010–2020Based in San Jose, CA, US· patent location history
2012–2020Patents assigned to WERNER JEREMY ISAAC NATHANIEL (8)· patent assignee history
2012–2013Patents assigned to BARCK RUSSELL (4)· patent assignee history
2012–2013Patents assigned to OBEREINER WILLY (3)· patent assignee history
2015–2020Patents assigned to SEAGATE TECHNOLOGY LLC (14)· patent assignee history
2021Based in Federal Way, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SEAGATE TECHNOLOGY LLC | 14 | 2015–2020 |
| WERNER JEREMY ISAAC NATHANIELself | 8 | 2012–2020 |
| SPANSION LLC | 7 | 2010–2013 |
| BARCK RUSSELL | 4 | 2012–2013 |
| OBEREINER WILLY | 3 | 2012–2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 23 | 2010–2020 |
| Federal Way, Washington, US | 2 | 2021 |