Inventor
Phil Knag
Inventor
Hillsboro, OR, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Nprimary
G06NComputing arrangements based on specific computational models33%
G06FElectric digital data processing25%
G11CStatic stores19%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%
G06GAnalogue computers4%
H03KPulse technique4%
G04FTime-interval measuring2%
H01LSemiconductor devices2%
H03MCoding2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
11,100,385Scalable free-running neuromorphic computer202111,062,203Neuromorphic computer with reconfigurable memory mapping for various neural network topologies202111,048,434Compute in memory circuits with time-to-digital computation202111,042,795Sparse neuromorphic processor202111,016,701Oscillator circuitry to facilitate in-memory computation202111,017,288Spike timing dependent plasticity in neuromorphic hardware202110,956,813Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions202110,922,607Event driven and time hopping neural network202110,884,957Pipeline circuit architecture to provide in-memory computation functionality202110,877,752Techniques for current-sensing circuit design for compute-in-memory202010,860,682Binary, ternary and bit serial compute-in-memory circuits202010,831,446Digital bit-serial multi-multiply-and-accumulate compute in memory202010,825,509Full-rail digital read compute-in-memory circuit202010,748,603In-memory multiply and accumulate with global charge-sharing202010,713,558Neural network with reconfigurable sparse connectivity and online learning202010,705,967Programmable interface to in-memory cache processor202010,642,922Binary, ternary and bit serial compute-in-memory circuits202010,565,138Memory device with multiple memory arrays to facilitate in-memory computation202010,248,906Neuromorphic circuits for storing and generating connectivity information2019Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2019–2021Patents assigned to INTEL CORP (18)· patent assignee history
2019–2021Based in Hillsboro, OR, US· patent location history
2020Patents assigned to CHEN GREGORY K (1)· patent assignee history
2020Patents assigned to KNAG PHIL (1)· patent assignee history
2020Patents assigned to KRISHNAMURTHY RAM (1)· patent assignee history
2020Patents assigned to KUMAR RAGHAVAN (1)· patent assignee history
2020–2021Based in Portland, OR, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 18 | 2019–2021 |
| CHEN GREGORY K | 1 | 2020 |
| KNAG PHILself | 1 | 2020 |
| KRISHNAMURTHY RAM | 1 | 2020 |
| KUMAR RAGHAVAN | 1 | 2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 13 | 2019–2021 |
| Portland, OR, US | 6 | 2020–2021 |