Inventor
Cheng-Wei Cheng
Inventor
White Plains, NY, US
Overview
Patents· 118 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices23%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h106%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation5%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light5%
H10HInorganic light-emitting semiconductor devices having potential barriers4%
G02BOptical elements, systems or apparatus2%
Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%
C30BSingle-crystal growth1%
PatentTitleYear
10,756,506III-V photonic integrated circuits on silicon substrate202010,755,925Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films202010,686,090Wafer bonded solar cells and fabrication methods202010,600,891Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth202010,601,199Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same202010,546,926III-V semiconductor devices with selective oxidation202010,489,947Mobile device, application display method, and non-transitory computer readable storage medium201910,460,937Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films201910,460,948Stress assisted wet and dry epitaxial lift off201910,453,683Post growth heteroepitaxial layer separation for defect reduction in heteroepitaxial films201910,439,356III-V photonic integrated circuits on silicon substrate201910,388,522Selective epitaxy using epitaxy-prevention layers201910,367,060III-V semiconductor devices with selective oxidation201910,304,947Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth201910,256,608Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201910,217,659Dual isolation fin and method of making201910,217,632Integration of III-V compound materials on silicon201910,205,003Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers201910,141,719Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,135,226Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same201810,128,343III-V MOSFET with self-aligned diffusion barrier201810,122,153Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,083,986CMOS with middle of line processing of III-V material on mandrel201810,083,987CMOS with middle of line processing of III-V material on mandrel201810,043,663Enhanced defect reduction for heteroepitaxy by seed shape engineering201810,037,989III-V lateral bipolar integration with silicon201810,014,377III-V field effect transistor on a dielectric layer20189,984,873Preparation of low defect density of III-V on Si for device fabrication20189,966,735III-V lasers with integrated silicon photonic circuits20189,947,755III-V MOSFET with self-aligned diffusion barrier20189,947,533Selective epitaxy using epitaxy-prevention layers20189,941,363III-V transistor device with self-aligned doped bottom barrier20189,882,021'Planar III-V field effect transistor (FET) on dielectric layer'20189,864,135'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material'20189,865,469'Epitaxial lift-off process with guided etching'20189,853,109III-V MOSFET with self-aligned diffusion barrier20179,818,901'Wafer bonded solar cells and fabrication methods'20179,793,405'Semiconductor lateral sidewall growth from a semiconductor pillar'20179,773,812'Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same'20179,773,903'Asymmetric III-V MOSFET on silicon substrate'20179,735,175'Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same'20179,726,819'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20179,722,031'Reduced current leakage semiconductor device'20179,711,617'Dual isolation fin and method of making'20179,704,958'III-V field effect transistor on a dielectric layer'20179,653,308'Epitaxial lift-off process with guided etching'20179,627,482'Reduced current leakage semiconductor device'20179,608,160'Polarization free gallium nitride-based photonic devices on nanopatterned silicon'20179,595,805'III-V photonic integrated circuits on silicon substrate'20179,590,393'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20179,570,296'Preparation of low defect density of III-V on Si for device fabrication'20179,564,494'Enhanced defect reduction for heteroepitaxy by seed shape engineering'20179,553,166'Asymmetric III-V MOSFET on silicon substrate'20179,530,643'Selective epitaxy using epitaxy-prevention layers'20169,529,956'Active region design layout'20169,515,165'III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture'20169,508,640'Multiple via structure and method'20169,508,550'Preparation of low defect density of III-V on Si for device fabrication'20169,496,347'Graded buffer epitaxy in aspect ratio trapping'20169,495,019'Display method of mobile device selection and terminal device'20169,472,411'Spalling using dissolvable release layer'20169,412,744'III-V CMOS integration on silicon substrate via embedded germanium-containing layer'20169,407,066'III-V lasers with integrated silicon photonic circuits'20169,406,566'Integration of III-V compound materials on silicon'20169,401,583'Laser structure on silicon using aspect ratio trapping growth'20169,397,161'Reduced current leakage semiconductor device'20169,395,489'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxially formed material'20169,397,226'Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts'20169,391,144'Selective gallium nitride regrowth on (100) silicon'20169,368,407'Crack control for substrate separation'20169,349,591'Crystal formation on non-lattice matched substrates'20169,344,200'Complementary metal oxide semiconductor device with III-V optical interconnect having III-V epitaxial semiconductor material formed using lateral overgrowth'20169,337,281'Planar semiconductor growth on III-V material'20169,324,564'Spalling with laser-defined spall edge regions'20169,287,362'Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts'20169,287,115'Planar III-V field effect transistor (FET) on dielectric layer'20169,263,626'Crystalline thin film photovoltaic cell'20169,236,251'Heterogeneous integration of group III nitride on silicon for advanced integrated circuits'20169,123,569'Complementary metal-oxide-semiconductor structure with III-V and silicon germanium transistors on insulator'20159,099,381'Selective gallium nitride regrowth on (100) silicon'20159,093,532'Overlapped III-V finFET with doped semiconductor extensions'20159,087,775'Planar semiconductor growth on III-V material'20159,087,905'Transistor formation using cold welding'20159,082,689'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20159,082,690'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20159,079,269'Spalling with laser-defined spall edge regions'20159,059,288'Overlapped III-V finfet with doped semiconductor extensions'20159,059,075'Selective gallium nitride regrowth on (100) silicon'20159,059,231'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,232'T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator'20159,059,073'Method for controlled removal of a semiconductor device layer from a base substrate'20159,053,930'Heterogeneous integration of group III nitride on silicon for advanced integrated circuits'20159,054,192'Integration of Ge-containing fins and compound semiconductor fins'20159,048,173'Dual phase gallium nitride material formation on (100) silicon'20159,040,392'Method for controlled removal of a semiconductor device layer from a base substrate'20158,975,635'Co-integration of elemental semiconductor devices and compound semiconductor devices'20158,946,054'Crack control for substrate separation'20158,941,147'Transistor formation using cold welding'20158,937,299'III-V finFETs on silicon substrate'20158,907,381'Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer'20148,889,541'Reduced short channel effect of III-V field effect transistor via oxidizing aluminum-rich underlayer'20148,853,529'Flexible III-V solar cell structure'20148,841,177'Co-integration of elemental semiconductor devices and compound semiconductor devices'20148,828,824'III-V field effect transistory (FET) and III-V semiconductor on insulator (IIIVOI) FET, integrated circuit (IC) chip and method of manufacture'20148,822,317'Self-aligned III-V MOSFET diffusion regions and silicide-like alloy contact'20148,796,120'High throughput epitaxial lift off for flexible electronics'20148,679,947'Self-formation of high-density defect-free and aligned nanostructures'20148,624,361'Self-formation of high-density defect-free and aligned nanostructures'20148,604,519'Self-aligned III-V field effect transistor (FET) and integrated circuit (IC) chip'20138,569,097'Flexible III-V solar cell structure'20138,541,315'High throughput epitaxial lift off for flexible electronics'20138,492,187'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20138,482,033'High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate'20138,466,493'Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture'20138,402,615'Hook structure and injection molded hook strap including the same'2013D0659407'Closure tape for disposable absorbent article'2012D0658044'Hook of hook-and-loop fastener'2012D0654355'Cable tie'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2013Based in Chang Hua Hsien, TW· patent location history
2013–2020Patents assigned to IBM (104)· patent assignee history
2013–2017Patents assigned to CHENG CHENG-WEI (13)· patent assignee history
2013–2017Patents assigned to SHIU KUEN-TING (10)· patent assignee history
2013–2017Patents assigned to SADANA DEVENDRA K (7)· patent assignee history
2013–2020Based in White Plains, NY, US· patent location history
2016–2018Patents assigned to GLOBALFOUNDRIES INC (7)· patent assignee history
2016Based in Taichung, TW· patent location history
2016Based in Shenzhen, CN· patent location history
2019Based in Taoyuan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 104 | 2013–2020 |
| CHENG CHENG-WEIself | 13 | 2013–2017 |
| SHIU KUEN-TING | 10 | 2013–2017 |
| GLOBALFOUNDRIES INC | 7 | 2016–2018 |
| SADANA DEVENDRA K | 7 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| White Plains, New York, US | 111 | 2013–2020 |
| Chang Hua Hsien, TW | 4 | 2012–2013 |
| Taoyuan, TW | 1 | 2019 |
| Taichung, TW | 1 | 2016 |
| Shenzhen, CN | 1 | 2016 |