Inventor
Aelan Mosden
Inventor
Poughkeepsie, NY, US
Overview
Patents· 15 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1030%
H01LSemiconductor devices23%
H10DInorganic electric semiconductor devices15%
H01JElectric discharge tubes or discharge lamps10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
B82YSpecific uses or applications of nanostructures5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
B08BCleaning in general3%
C23CCoating metallic material3%
PatentTitleYear
10,971,372Gas phase etch with controllable etch selectivity of Si-containing arc or silicon oxynitride to different films or masks202110,923,356Gas phase etch with controllable etch selectivity of silicon-germanium alloys202110,600,687Process integration techniques using a carbon layer to form self-aligned structures202010,580,660Gas phase etching system and method202010,573,564Method for fabricating NFET and PFET nanowire devices202010,290,553System and method of determining process completion of post heat treatment of a dry etch process20199,984,890Isotropic silicon and silicon-germanium etching with tunable selectivity20189,748,110'Method and system for selective spacer etch for multi-patterning schemes'20178,809,169'Multi-layer pattern for alternate ALD processes'20148,673,725'Multilayer sidewall spacer for seam protection of a patterned structure'20148,664,102'Dual sidewall spacer for seam protection of a patterned structure'20147,959,970'System and method of removing chamber residues from a plasma processing system in a dry cleaning process'20117,291,446'Method and system for treating a hard mask to improve etch characteristics'20077,226,868'Method of etching high aspect ratio features'20077,097,779'Processing system and method for chemically treating a TERA layer'2006Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2006–2021Patents assigned to TOKYO ELECTRON LTD (15)· patent assignee history
2006–2021Based in Poughkeepsie, NY, US· patent location history
2014Patents assigned to MOSDEN AELAN (3)· patent assignee history
2014Patents assigned to O'MEARA DAVID L (3)· patent assignee history
2014Patents assigned to CHOU PAO-HWA (2)· patent assignee history
2014Patents assigned to CONTI RICHARD A (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TOKYO ELECTRON LTD | 15 | 2006–2021 |
| MOSDEN AELANself | 3 | 2014 |
| O'MEARA DAVID L | 3 | 2014 |
| CHOU PAO-HWA | 2 | 2014 |
| CONTI RICHARD A | 2 | 2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 15 | 2006–2021 |