Inventor
Vivek Garg
Inventor
Folsom, CA, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use25%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications13%
H04LTransmission of digital information, e.g. telegraphic communication4%
G01CMeasuring distances, levels or bearings2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
G08GTraffic control systems2%
H04MTelephonic communication2%
A47KSanitary equipment1%
A61BDiagnosis1%
PatentTitleYear
10,877,549Configuring power management functionality in a processor202010,877,977Generating a relevance score for direct digital messages based on crowdsourced information and social-network signals202010,757,259Custom calling using a messaging system202010,722,120Sensor platform array that moves sensor platforms to conform to the shape of the subject to be monitored202010,708,383Identifying profile information of senders of direct digital messages202010,607,191Efficient calendar creation202010,545,793Thread scheduling using processing engine information202010,510,259Method and system for scheduling a driver service provider for one or more third parties201910,474,208Systems, methods and devices for using thermal margin of a core in a processor201910,203,741Configuring power management functionality in a processor201910,191,532Configuring power management functionality in a processor201910,055,996Method and system for scheduling a driver service provider for one or more third parties201810,048,744Apparatus and method for thermal management in a multi-chip package20189,977,482Method and apparatus for setting an I/O bandwidth-based processor frequency floor20189,910,470'Controlling telemetry data communication in a processor'20189,760,409'Dynamically modifying a power/performance tradeoff based on a processor utilization'20179,760,155'Configuring power management functionality in a processor'20179,710,041'Masking a power state of a core of a processor'20179,606,595'Microprocessor-assisted auto-calibration of voltage regulators'20179,557,804'Dynamic power limit sharing in a platform'20179,547,027'Dynamically measuring power consumption in a processor'20179,501,129'Dynamically adjusting power of non-core processor circuitry including buffer circuitry'20169,494,996'Processor having frequency of operation information for guaranteed operation under high temperature events'20169,471,118'Uncore thermal management'20169,405,351'Performing frequency coordination in a multiprocessor system'20169,372,524'Dynamically modifying a power/performance tradeoff based on processor utilization'20169,268,393'Enforcing a power consumption duty cycle in a processor'20169,235,244'Configuring power management functionality in a processor'20169,158,351'Dynamic power limit sharing in a platform'20159,141,426'Processor having per core and package level P0 determination functionality'20159,075,614'Managing power consumption in a multi-core processor'20159,069,555'Managing power consumption in a multi-core processor'20158,984,313'Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator'20158,914,650'Dynamically adjusting power of non-core processor circuitry including buffer circuitry'20148,700,937'Uncore thermal management'20148,244,985'Store performance in strongly ordered microprocessor architecture'20127,836,229'Synchronizing control and data paths traversed by a data transaction'20107,831,776'Dynamic allocation of home coherency engine tracker resources in link based computing system'20107,694,161'Uncore thermal management'20107,600,080'Avoiding deadlocks in a multiprocessor system'20097,484,045'Store performance in strongly-ordered microprocessor architecture'20097,076,609'Cache sharing for a chip multiprocessor or multiprocessing system'20066,976,131'Method and apparatus for shared cache coherency for a chip multiprocessor or multiprocessor system'20056,842,180'Opportunistic sharing of graphics resources to enhance CPU performance in an integrated microprocessor'20056,718,440'Memory access latency hiding with hint buffer'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2020Patents assigned to INTEL CORP (38)· patent assignee history
2004–2020Based in Folsom, CA, US· patent location history
2005Based in Rancho Cordova, CA, US· patent location history
2012–2020Patents assigned to GARG VIVEK (11)· patent assignee history
2015–2018Patents assigned to VARMA ANKUSH (5)· patent assignee history
2015–2018Patents assigned to ROWLAND MARTIN T (4)· patent assignee history
2015–2018Patents assigned to SISTLA KRISHNAKANTH V (4)· patent assignee history
2018–2019Based in San Mateo, CA, US· patent location history
2020Based in Seattle, WA, US· patent location history
2020Based in Murray, UT, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 38 | 2004–2020 |
| GARG VIVEKself | 11 | 2012–2020 |
| VARMA ANKUSH | 5 | 2015–2018 |
| ROWLAND MARTIN T | 4 | 2015–2018 |
| SISTLA KRISHNAKANTH V | 4 | 2015–2018 |
Locations
| Location | Patents | Span |
|---|---|---|
| Folsom, California, US | 37 | 2004–2020 |
| Seattle, Washington, US | 4 | 2020 |
| San Mateo, California, US | 2 | 2018–2019 |
| Murray, UT, US | 1 | 2020 |
| Rancho Cordova, California, US | 1 | 2005 |