Inventor

Effendi Leobandung

Inventor
Stormville, NY, US

Overview

444→
Patents
2000–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 444 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary
H01LSemiconductor devices26%
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1014%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
H10BElectronic memory devices4%
B82YSpecific uses or applications of nanostructures3%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation2%
H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light2%
G06FElectric digital data processing2%
G02BOptical elements, systems or apparatus2%
PatentTitleYear
11,114,479Optoelectronics and CMOS integration on GOI substrate202111,107,821Semiconductor structures with deep trench capacitor and methods of manufacture202111,088,264Self-aligned channel-only semiconductor-on-insulator field effect transistor202111,079,337Secure wafer inspection and identification202111,055,610Circuit for CMOS based resistive processing unit202111,055,611Circuit for CMOS based resistive processing unit202111,055,607Neural network using floating gate transistor202111,056,493Semiconductor structures with deep trench capacitor and methods of manufacture202111,037,834Simple contact over gate on active area202111,031,346Advanced wafer security method including pattern and wafer verifications202111,024,636Vertical 3D stack NOR device202111,018,123Multi-chip modules202111,011,651Tight pitch stack nanowire isolation202110,998,311Fabricating gate-all-around transistors having high aspect ratio channels and reduced parasitic capacitance202110,997,490Battery-based neural network weights202110,984,306Battery-based neural network weights202110,985,280Threshold voltage control using channel digital etch202110,978,593Threshold voltage control using channel digital etch202110,971,604Gate all around fin field effect transistor202110,957,780Non-uniform gate dielectric for U-shape MOSFET202110,957,802Methods of forming tight pitch stack nanowire isolation202110,957,596Caterpillar trenches for efficient wafer dicing202110,957,665Direct C4 to C4 bonding without substrate202110,949,745Smart logic device202110,930,579Self-contained liquid cooled semiconductor packaging202110,923,445Monolithic decoupling capacitor between solder bumps202110,916,468Semiconductor device with buried local interconnects202110,909,444Floating gate for neural network inference202110,909,445Floating gate for neural network inference202110,903,422Vertically oriented memory structure202110,900,953DNA sequencing using MOSFET transistors202110,896,979Compact vertical injection punch through floating gate analog memory and a manufacture thereof202110,892,164Dual hard mask replacement gate202110,891,368Dynamic embedded integrated circuit in trackable item202110,886,281Transistor and capacitor structures for analog memory neural network202110,879,568Thin film lithium ion battery202010,872,954Sidewall image transfer nanosheet202010,833,010Integration of artificial intelligence devices202010,833,156Self-forming spacers using oxidation202010,832,942Non-embedded silicon bridge chip for multi-chip module202010,818,838Phase change memory202010,802,071Elemental mercury-containing probe card202010,804,107Well and punch through stopper formation using conformal doping202010,784,169Self-aligned hard mask for epitaxy protection202010,784,292Optoelectronics and CMOS integration on GOI substrate202010,777,567Epitaxy lateral overgrowth for 3D NAND202010,769,327Integrated circuit authentication using mask fingerprinting202010,763,340Growing Groups III-V lateral nanowire channels202010,741,611Resistive processing units with complementary metal-oxide-semiconductor non-volatile analog memory202010,741,532Multi-chip modules202010,741,560High resistance readout FET for cognitive device202010,714,419Non-planar metal-insulator-metal capacitor formation202010,700,017Interchip backside connection202010,679,904Stacked vertical devices202010,672,983Compact resistive random access memory integrated with a pass gate transistor202010,658,483Non-planar field effect transistor devices with wrap-around source/drain contacts202010,658,484Non-planar field effect transistor devices with wrap-around source/drain contacts202010,629,680Sidewall image transfer nanosheet202010,629,601Transistor and capacitor structures for analog memory neural network202010,622,283Self-contained liquid cooled semiconductor packaging202010,622,207Low external resistance channels in III-V semiconductor devices202010,615,178Dual-material mandrel for epitaxial crystal growth on silicon202010,605,985Integration of bonded optoelectronics, photonics waveguide and VLSI SOI202010,607,838Well and punch through stopper formation using conformal doping202010,601,199Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same202010,600,783Self-cut sidewall image transfer process202010,600,912Self-aligned replacement metal gate spacerless vertical field effect transistor202010,600,891Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth202010,600,795Integration of floating gate memory and logic device in replacement gate flow202010,593,784Double patterning epitaxy Fin202010,586,853Non-planar field effect transistor devices with wrap-around source/drain contacts202010,580,900Nanosheet channel post replacement gate process202010,573,558Caterpillar trenches for efficient wafer dicing202010,566,247Local wiring in between stacked devices202010,566,417Self-forming spacers using oxidation202010,559,493Multifunction single via patterning202010,546,878Asymmetric junction engineering for narrow band gap MOSFET202010,545,131DNA sequencing using MOSFET transistors202010,546,926III-V semiconductor devices with selective oxidation202010,535,662Semiconductor structures including an integrated FinFET with deep trench capacitor and methods of manufacture202010,529,624Simple contact over gate on active area202010,529,739Asymmetric band gap junctions in narrow band gap MOSFET202010,522,686Vertical thin film transistor201910,483,156Non-embedded silicon bridge chip for multi-chip module201910,475,701Mixed wire structure and method of making the same201910,461,194Threshold voltage control using channel digital etch201910,452,973Smart logic device201910,454,239Wafer scale monolithic integration of lasers, modulators, and other optical components using ALD optical coatings201910,446,490Junctionless back end of the line via contact201910,438,913Monolithic decoupling capacitor between solder bumps201910,418,493Tight pitch stack nanowire isolation201910,396,147Grated MIM capacitor to improve capacitance201910,389,090Lateral growth of edge-emitting lasers201910,367,060III-V semiconductor devices with selective oxidation201910,361,300Asymmetric vertical device201910,361,207Semiconductor structures with deep trench capacitor and methods of manufacture201910,347,717Fabrication of nanowire vertical gate devices201910,347,739Extended contact area using undercut silicide extensions201910,347,657Semiconductor circuit including nanosheets and fins on the same wafer201910,326,004Double patterning epitaxy fin201910,325,852Self-aligned vertical transistor with local interconnect201910,315,933Pressure differential water distiller201910,319,811Semiconductor device including fin having condensed channel region201910,319,838III-V fin generation by lateral growth on silicon sidewall201910,319,860Overlap capacitance nanowire201910,312,160Gate-last semiconductor fabrication with negative-tone resolution enhancement201910,311,225Dynamic embedded integrated circuit in trackable item201910,303,998Floating gate for neural network inference201910,304,947Smoothing surface roughness of III-V semiconductor fins formed from silicon mandrels by regrowth201910,304,839Metal strap for DRAM/FinFET combination201910,291,414SRAM as physically unclonable function201910,283,537Optoelectronics and CMOS integration on GOI substrate201910,276,685Heterojunction tunnel field effect transistor fabrication using limited lithography steps201910,269,806Semiconductor structures with deep trench capacitor and methods of manufacture201910,269,956Asymmetric vertical device201910,261,067Method of forming a field effect based nanopore device201910,256,319Non-uniform gate dielectric for U-shape MOSFET201910,256,608Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201910,249,632Simple integration of non-volatile memory and complementary metal oxide semiconductor201910,249,722Reduced parasitic capacitance with slotted contact201910,246,745DNA sequencing detection field effect transistor201910,249,736Aspect ratio trapping in channel last process201910,243,002Asymmetric band gap junctions in narrow band gap MOSFET201910,242,991Highly compact floating gate analog memory201910,224,415Integrated vertical nanowire memory201910,217,512Unit cell with floating gate MOSFET for analog memory201910,217,659Dual isolation fin and method of making201910,218,150Wafer scale monolithic integration of lasers, modulators, and other optical components using ALD optical coatings201910,211,225FinFET devices wit multiple channel lengths201910,211,109Local wiring in between stacked devices201910,205,003Surface roughness of III-V fin formed on silicon sidewall by implementing sacrificial buffers201910,204,907Metal-insulator-metal capacitor analog memory unit cell201910,192,864Lateral BiCMOS replacement metal gate201910,177,047Trench gate first CMOS201910,177,254III-V compound semiconductor channel post replacement gate201910,170,551Sidewall image transfer nanosheet201910,170,558Localized and self-aligned punch through stopper doping for finFET201910,168,473Integration of bonded optoelectronics, photonics waveguide and VLSI SOI201910,141,277Monolithic decoupling capacitor between solder bumps201810,141,719Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,141,048Stack capacitor for neural network201810,135,226Resonant cavity strained Group III-V photodetector and LED on silicon substrate and method to fabricate same201810,134,472Floating gate architecture for deep neural network application201810,128,199Interchip backside connection201810,122,153Resonant cavity strained group III-V photodetector and LED on silicon substrate and method to fabricate same201810,109,575Non-planar metal-insulator-metal capacitor formation201810,103,218Densely stacked metal-insulator-metal capacitor and method of forming the same201810,103,237Inverted MOSFET with scaling advantage201810,103,242Growing groups III-V lateral nanowire channels201810,096,697III-V FIN generation by lateral growth on silicon sidewall201810,096,975Laterally grown edge emitting laser201810,096,689Low end parasitic capacitance FinFET201810,090,340Optoelectronic devices with back contact201810,090,165Method to improve finFET cut overlay201810,090,562Thin film lithium ion battery201810,090,429Integrated on chip detector and zero waveguide module structure for use in DNA sequencing201810,083,986CMOS with middle of line processing of III-V material on mandrel201810,083,987CMOS with middle of line processing of III-V material on mandrel201810,079,249Finfet devices with multiple channel lengths201810,079,234Metal-insulator-metal capacitor analog memory unit cell201810,068,922FinFET devices with multiple channel lengths201810,068,994III-V fin generation by lateral growth on silicon sidewall201810,068,967Self-forming spacers using oxidation201810,061,617Smart memory analog DRAM201810,062,752Fabrication of nanowire vertical gate devices201810,056,408Structure and method to form a FinFET device201810,050,123Integrated vertical nanowire memory201810,047,393DNA sequencing using MOSFET transistors201810,050,039Semiconductor structures with deep trench capacitor and methods of manufacture201810,042,968Semiconductor structures with deep trench capacitor and methods of manufacture201810,043,863Grated MIM capacitor to improve capacitance201810,037,989III-V lateral bipolar integration with silicon201810,030,265DNA sequencing using MOSFET transistors201810,032,793Asymmetric junction engineering for narrow band gap MOSFET201810,025,029Integration of bonded optoelectronics, photonics waveguide and VLSI SOI201810,020,051Stack capacitor for neural network201810,014,372Vertical gate-all-around transistor with top and bottom source/drain epitaxy on a replacement nanowire, and method of manufacturing the same201810,008,586Dual fill silicon-on-nothing field effect transistor201810,007,057Integration of bonded optoelectronics, photonics waveguide and VLSI SOI201810,001,598Integration of bonded optoelectronics, photonics waveguide and VLSI SOI20189,997,413Stacked vertical devices20189,988,678DNA sequencing detection field effect transistor20189,984,880Well and punch through stopper formation using conformal doping20189,985,100Localized and self-aligned punch through stopper doping for finFET20189,985,130Salicide formation on replacement metal gate finFET devices20189,985,032Selectively degrading current resistance of field effect transistor devices20189,977,185Integration of bonded optoelectronics, photonics waveguide and VLSI SOI20189,953,857Semiconductor device with buried local interconnects20189,947,969Thin film lithium ion battery20189,945,836Field effect based nanopore device20189,941,118Dense vertical nanosheet20189,935,236Monolithic nano-cavity light source on lattice mismatched semiconductor substrate20189,935,178Self-aligned channel-only semiconductor-on-insulator field effect transistor20189,935,200Annealed metal source drain overlapping the gate of a fin field effect transistor20189,929,255'Robust gate spacer for semiconductor devices'20189,917,059'Self-aligned vertical transistor with local interconnect'20189,917,151'Forming multi-stack nanowires using a common release material'20189,917,014'Vertical air gap subtractive etch back end metal'20189,911,602'Embedded gallium-nitride in silicon'20189,905,475'Self-aligned hard mask for epitaxy protection'20189,904,009'Electrical and optical through-silicon-via (TSV)'20189,899,397'Integration of floating gate memory and logic device in replacement gate flow'20189,893,489'Wafer scale monolithic integration of lasers, modulators, and other optical components using ALD optical coatings'20189,881,930'Simple integration of non-volatile memory and complementary metal oxide semiconductor'20189,882,047'Self-aligned replacement metal gate spacerless vertical field effect transistor'20189,881,919'Well and punch through stopper formation using conformal doping'20189,859,280'Selectively degrading current resistance of field effect transistor devices'20189,859,685'Small aperture formation for facilitating optoelectronic device integration with defective semiconductor materials'20189,859,397'Growing groups III-V lateral nanowire channels'20189,837,453Self-sufficient chip with photovoltaic power supply on back of wafer20179,825,143'Single spacer tunnel on stack nanowire'20179,818,761'Selective oxidation for making relaxed silicon germanium on insulator structures'20179,812,323'Low external resistance channels in III-V semiconductor devices'20179,793,405'Semiconductor lateral sidewall growth from a semiconductor pillar'20179,786,566'Aspect ratio for semiconductor on insulator'20179,786,767'Air gap contact formation for reducing parasitic capacitance'20179,780,166'Forming multi-stack nanowires using a common release material'20179,779,355'Back propagation gates and storage capacitor for neural networks'20179,773,812'Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same'20179,772,463'Intra chip optical interconnect structure'20179,773,865'Self-forming spacers using oxidation'20179,773,903'Asymmetric III-V MOSFET on silicon substrate'20179,761,721'Field effect transistors with self-aligned extension portions of epitaxial active regions'20179,761,698'Air gap contact formation for reducing parasitic capacitance'20179,754,969'Dual-material mandrel for epitaxial crystal growth on silicon'20179,754,935'Raised metal semiconductor alloy for self-aligned middle-of-line contact'20179,754,819'Interlevel airgap dielectric'20179,742,147'Monolithic integrated photonics with lateral bipolar and BiCMOS'20179,735,175'Integrated circuit with heterogeneous CMOS integration of strained silicon germanium and group III-V semiconductor materials and method to fabricate same'20179,735,273'Method of forming a III-V compound semiconductor channel post replacement gate'20179,728,671'Monolithic nano-cavity light source on lattice mismatched semiconductor substrate'20179,722,031'Reduced current leakage semiconductor device'20179,722,022'Sidewall image transfer nanosheet'20179,716,160'Extended contact area using undercut silicide extensions'20179,716,367'Semiconductor optoelectronics and CMOS on sapphire substrate'20179,716,030'Aspect ratio for semiconductor on insulator'20179,716,056'Integrated circuit with back side inductor'20179,711,617'Dual isolation fin and method of making'20179,711,648'Structure and method for CMP-free III-V isolation'20179,704,866'Integrated circuit having dual material CMOS integration and method to fabricate same'20179,704,950'Method to form SOI fins on a bulk substrate with suspended anchoring'20179,698,239'Growing groups III-V lateral nanowire channels'20179,698,225'Localized and self-aligned punch through stopper doping for finFET'20179,687,181'Semiconductor device to be embedded within a contact lens'20179,691,709'Semiconductor device security'20179,685,521'Lowering parasitic capacitance of replacement metal gate processes'20179,685,501'Low parasitic capacitance finFET device'20179,685,410'Semiconductor device security'20179,685,329'Embedded gallium-nitride in silicon'20179,679,775'Selective dopant junction for a group III-V semiconductor device'20179,673,056'Method to improve finFET cut overlay'20179,666,748'Integrated on chip detector and zero waveguide module structure for use in DNA sequencing'20179,660,069'Group III nitride integration with CMOS technology'20179,653,347'Vertical air gap subtractive etch back end metal'20179,653,464'Asymmetric band gap junctions in narrow band gap MOSFET'20179,647,091'Annealed metal source drain overlapping the gate'20179,640,442'CMOS fin integration on SOI substrate'20179,640,536'Method to make dual material finFET on same substrate'20179,627,271'III-V compound semiconductor channel material formation on mandrel after middle-of-the-line dielectric formation'20179,627,478'Integrated vertical nanowire memory'20179,627,266'Dual-semiconductor complementary metal-oxide-semiconductor device'20179,627,276'Self-aligned low defect segmented III-V finFET'20179,627,482'Reduced current leakage semiconductor device'20179,620,643'Reducing parasitic capacitance and resistance in finFET'20179,613,963'Dual material finFET on single substrate'20179,614,042'Heterojunction tunnel field effect transistor fabrication using limited lithography steps'20179,608,099'Nanowire semiconductor device'20179,601,385'Method of making a dual strained channel semiconductor device'20179,601,599'Aspect ratio for semiconductor on insulator'20179,601,476'Optoelectronics and CMOS integration on GOI substrate'20179,595,445'Floating body storage device employing a charge storage trench'20179,590,057'Reduced parasitic capacitance with slotted contact'20179,590,085'Method and structure for III-V FinFET'20179,577,096'Salicide formation on replacement metal gate finFet devices'20179,576,096'Semiconductor structures including an integrated finFET with deep trench capacitor and methods of manufacture'20179,570,554'Robust gate spacer for semiconductor devices'20179,570,449'Metal strap for DRAM/FinFET combination'20179,564,506'Low end parasitic capacitance FinFET'20179,564,526'Group III nitride integration with CMOS technology'20179,553,166'Asymmetric III-V MOSFET on silicon substrate'20179,553,107'Shallow extension junction'20179,548,358'Dual fill silicon-on-nothing field effect transistor'20179,548,421'Optoelectronic devices with back contact'20179,543,463'Signal distribution in integrated circuit using optical through silicon via'20179,536,832'Junctionless back end of the line via contact'20179,536,739'Self-cut sidewall image transfer process'20179,536,775'Aspect ratio for semiconductor on insulator'20179,530,665'Protective trench layer and gate spacer in finFET devices'20169,525,069'Structure and method to form a FinFET device'20169,515,070'Replacement metal gate'20169,515,165'III-V field effect transistor (FET) with reduced short channel leakage, integrated circuit (IC) chip and method of manufacture'20169,515,090'Method to form dual channel group III-V and Si/Ge FINFET CMOS and integrated circuit fabricated using the method'20169,508,833'Punch through stopper for semiconductor device'20169,502,500'Forming multi-stack nanowires using a common release material'20169,502,506'Structure for FinFET fins'20169,496,447'Signal distribution in integrated circuit using optical through silicon via'20169,496,399'FinFET devices with multiple channel lengths'20169,496,379'Method and structure for III-V FinFET'20169,484,250'Air gap contact formation for reducing parasitic capacitance'20169,478,708'Embedded gallium—nitride in silicon'2016

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2001–2021Patents assigned to IBM (427)· patent assignee history
2001–2017Based in Wappingers Falls, NY, US· patent location history
2012–2019Patents assigned to LEOBANDUNG EFFENDI (17)· patent assignee history
2013–2015Patents assigned to BASKER VEERARAGHAVAN S (6)· patent assignee history
2013–2015Patents assigned to YAMASHITA TENKO (6)· patent assignee history
2013–2021Based in Stormville, NY, US· patent location history
2014–2015Based in Wappinger Falls, NY, US· patent location history
2015–2019Patents assigned to GLOBALFOUNDRIES INC (13)· patent assignee history
2017–2018Based in Stormvile, NY, US· patent location history
2018–2021Based in Yorktown Heights, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM4272001–2021
LEOBANDUNG EFFENDIself172012–2019
GLOBALFOUNDRIES INC132015–2019
BASKER VEERARAGHAVAN S62013–2015
YAMASHITA TENKO62013–2015
Locations
LocationPatentsSpan
Stormville, New York, US3532013–2021
Wappingers Falls, New York, US762001–2017
Yorktown Heights, New York, US52018–2021
Wappinger Falls, New York, US52014–2015
Stormvile, New York, US22017–2018