Inventor
Shuo-Mao Chen
Inventor
New Taipei, TW
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H01LSemiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%
H10DInorganic electric semiconductor devices8%
G06FElectric digital data processing2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes1%
H05KPrinted circuits1%
B28DWorking stone or stone-like materials1%
G01SRadio direction-finding1%
G06KGraphical data reading1%
PatentTitleYear
10,915,718Radio frequency positioning system202110,867,924Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing202010,867,925Method for forming chip package structure202010,804,244Semiconductor package structure and method of manufacturing the same202010,784,220Plurality of semiconductor devices encapsulated by a molding material attached to a redistribution layer202010,770,437Semiconductor package and manufacturing method of the same202010,763,239Multi-chip wafer level packages and methods of forming the same202010,741,404Package structure and method of manufacturing the same202010,741,537Semiconductor structure and manufacturing method thereof202010,714,463Method of forming semicondcutor device package202010,700,032Package with passive devices and method of forming the same202010,665,473Package structure and method of fabricating the same202010,636,747Semiconductor package structure202010,546,830Chip package structure202010,535,597Semiconductor structure and manufacturing method thereof202010,535,632Semiconductor package structure and method of manufacturing the same202010,515,827Method for forming chip package with recessed interposer substrate201910,515,875Interconnect structure for package-on-package devices201910,504,752Integrated passive device package and methods of forming same201910,504,880Method of forming semicondcutor device package201910,475,731Package with metal-insulator-metal capacitor and method of manufacturing the same201910,373,923Package with passive devices and method of forming the same201910,283,474Chip package structure and method for forming the same201910,276,484Package with metal-insulator-metal capacitor and method of manufacturing the same201910,276,551Semiconductor device package and method of forming semiconductor device package201910,269,685Interconnect structure for package-on-package devices201910,269,736Method of forming metal pads with openings in integrated circuits including forming a polymer extending into a metal pad201910,163,860Semiconductor package structure201810,050,024Semiconductor package and manufacturing method of the same20189,997,471Semiconductor package structure and manufacturing method thereof20189,960,106Package with metal-insulator-metal capacitor and method of manufacturing the same20189,922,903'Interconnect structure for package-on-package devices and a method of fabricating'20189,922,160'Integrated circuit stack verification method and system for performing the same'20189,911,629'Integrated passive device package and methods of forming same'20189,831,200Package with passive devices and method of forming the same20179,601,372'Method of forming metal pads with openings in integrated circuits including forming a polymer plug extending into a metal pad'20179,460,987'Interconnect structure for package-on-package devices and a method of fabricating'20169,379,069'Semiconductor arrangement comprising transmission line surrounded by magnetic layer'20169,275,923'Band pass filter for 2.5D/3D integrated circuit applications'20169,245,833'Metal pads with openings in integrated circuits'20169,048,222'Method of fabricating interconnect structure for package-on-package devices'20159,040,381'Packages with passive devices and methods of forming the same'20158,937,389'Semiconductor devices comprising GSG interconnect structures'20158,878,369'Low power/high speed TSV interface design'20148,809,996'Package with passive devices and method of forming the same'20148,680,647'Packages with passive devices and methods of forming the same'20148,390,078'Quadrangle MOS transistors'20138,324,713'Profile design for lateral-vertical bipolar junction transistor'20128,115,280'Four-terminal gate-controlled LVBJTs'20127,701,038'High-gain vertex lateral bipolar junction transistor'20106,903,644'Inductor device having improved quality factor'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (13)· patent assignee history
2005–2017Based in Hsinchu, TW· patent location history
2012–2016Patents assigned to CHEN SHUO-MAO (8)· patent assignee history
2012–2013Based in Hsin-Chuang, TW· patent location history
2014–2016Patents assigned to YEH DER-CHYANG (5)· patent assignee history
2014–2015Patents assigned to HOU SHANG-YUN (2)· patent assignee history
2014–2020Based in New Taipei, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (37)· patent assignee history
2021Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 37 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 13 | 2005–2016 |
| CHEN SHUO-MAOself | 8 | 2012–2016 |
| YEH DER-CHYANG | 5 | 2014–2016 |
| HOU SHANG-YUN | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| New Taipei, TW | 44 | 2014–2020 |
| Hsinchu, TW | 3 | 2005–2017 |
| Hsin-Chuang, TW | 3 | 2012–2013 |
| Tainan, TW | 1 | 2021 |