Inventor

Tao-Cheng Lu

Inventor

Kaohsiung, TW

Overview

1999–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 149 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

G11CStatic stores26%

H10BElectronic memory devices17%

H01LSemiconductor devices5%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%

G01RMeasuring electric variables2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

H02HEmergency protective circuit arrangements1%

H03KPulse technique1%

PatentTitleYear

11,034,689Small molecule protein arginine methyltransferase 5 (PRMT5) inhibitors and methods of treatment2021 10,934,408Surface modification method for polyether-ether-ketone material2021 10,018,038Drilling type sidewall coring apparatus2018 9,988,899Rock formation testing method and formation testing instrument2018 9,625,520'Latch-up test device and method for testing wafer under test'2017 9,509,137'Electrostatic discharge protection device'2016 9,460,928'Method for manufacturing semiconductor devices'2016 9,443,955'Semiconductor device and method for fabricating the same'2016 9,437,303'Programming method of memory array'2016 9,324,789'Memory device and method for fabricating the same'2016 9,281,195'Semiconductor structure'2016 9,208,892'Operation method of multi-level memory'2015 9,153,570'ESD tolerant I/O pad circuit including a surrounding well'2015 9,082,620'Semiconductor device'2015 8,952,484'Non-volatile memory having isolation structures in and above a substrate and manufacturing method thereof'2015 8,952,457'Electrostatic discharge protection circuit'2015 8,937,347'Non-volatile memory'2015 8,929,134'Method of programming a flash memory by enhancing the channel voltage of a program-inhibit bit line with a boosted inhibit scheme'2015 8,836,005'Memory array'2014 8,748,963'Non-volatile memory and manufacturing method thereof'2014 8,748,936'Methods and structures for electrostatic discharge protection'2014 8,675,322'Electrostatic discharge protection device'2014 8,605,507'Flash programming technology for improved margin and inhibiting disturbance'2013 8,501,591'Method for manufacturing a multiple-bit-per-cell memory'2013 8,411,506'Non-volatile memory and operating method of memory cell'2013 8,345,396'Electrostatic discharge protectors having increased RC delays'2013 8,338,880'Flash memory'2012 8,259,492'Method of reading dual-bit memory cell'2012 8,253,165'Structures for lowering trigger voltage in an electrostatic discharge protection device'2012 8,203,879'Non-volatile memory and operation method thereof'2012 8,164,112'Electostatic discharge protection circuit coupled on I/O pad'2012 8,098,522'Non-volatile memory and operation method thereof'2012 8,093,665'Semiconductor device and method for fabricating the same'2012 8,072,803'Memory device and methods for fabricating and operating the same'2011 8,014,203'Memory device and methods for fabricating and operating the same'2011 8,004,890'Operation method of non-volatile memory'2011 7,875,938'LDMOS device with multiple gate insulating members'2011 7,830,707'Method of reading dual-bit memory cell'2010 7,799,638'Method for forming a memory array'2010 7,692,968'Operation method of non-volatile memory and method of improving coupling interference from nitride-based memory'2010 7,573,102'ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad'2009 7,529,128'Integrated code and data flash memory'2009 7,486,568'Method and apparatus for protection from over-erasing nonvolatile memory cells'2009 7,486,086'Method for measuring intrinsic capacitance of a metal oxide semiconductor (MOS) device'2009 7,473,625'LDMOS device and method of fabrication'2009 7,348,625'Semiconductor device and method of manufacturing the same'2008 7,327,611'Method and apparatus for operating charge trapping nonvolatile memory'2008 7,307,888'Method and apparatus for operating nonvolatile memory in a parallel arrangement'2007 7,291,870'Electrostatic protection circuit'2007 7,224,619'Method and apparatus for protection from over-erasing nonvolatile memory cells'2007 7,193,274'ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad'2007 7,187,590'Method and system for self-convergent erase in charge trapping memory cells'2007 7,187,527'Electrostatic discharge conduction device and mixed power integrated circuits using same'2007 7,180,123'Method for programming programmable eraseless memory'2007 7,173,849'Method of programming and erasing multi-level flash memory'2007 7,158,411'Integrated code and data flash memory'2007 7,132,350'Method for manufacturing a programmable eraseless memory'2006 7,106,563'Electrostatic discharge protection circuit coupled on I/O pad'2006 7,057,938'Nonvolatile memory cell and operating method'2006 7,035,147'Overerase protection of memory cells for nonvolatile memory'2006 7,031,196'Nonvolatile semiconductor memory and operating method of the memory'2006 7,012,305'Electro-static discharge protection circuit for dual-polarity input/output pad'2006 7,002,849'Method for programming and erasing non-volatile memory with nitride tunneling layer'2006 6,996,011'NAND-type non-volatile memory cell and method for operating same'2006 6,965,504'ESD protection apparatus and method for a high-voltage input pad'2005 6,958,934'Method of programming and erasing multi-level flash memory'2005 6,947,267'RC controlled ESD circuits for mixed-voltage interface'2005 6,933,540'ESD protection apparatus and method for dual-polarity input pad'2005 6,919,604'Silicon controlled rectifier structure with guard ring controlled circuit'2005 6,919,607'Structure of two-bit mask read-only memory device and fabricating method thereof'2005 6,917,073'ONO flash memory array for improving a disturbance between adjacent memory cells'2005 6,914,819'Non-volatile flash memory'2005 6,882,575'Erasing method for non-volatile memory'2005 6,838,691'Chalcogenide memory and method of manufacturing the same'2005 6,834,263'NROM structure'2004 6,834,013'Method for programming and erasing non-volatile memory with nitride tunneling layer'2004 6,829,125'ESD protection circuit for multi-power and mixed-voltage integrated circuit'2004 6,829,174'Method of narrowing threshold voltage distribution'2004 6,829,175'Erasing method for non-volatile memory'2004 6,822,910'Non-volatile memory and operating method thereof'2004 6,812,099'Method for fabricating non-volatile memory having P-type floating gate'2004 6,808,995'Semiconductor device with minimal short-channel effects and low bit-line resistance'2004 6,809,915'Gate-equivalent-potential circuit and method for I/O ESD protection'2004 6,801,453'Method and apparatus of a read scheme for non-volatile memory'2004 6,791,146'Silicon controlled rectifier structure with guard ring controlled circuit'2004 6,790,730'Fabrication method for mask read only memory device'2004 6,785,163'Trim circuit and method for tuning a current level of a reference cell in a flash memory'2004 6,756,638'MOSFET structure with reduced junction capacitance'2004 6,724,677'ESD device used with high-voltage input pad'2004 6,720,614'Operation method for programming and erasing a data in a P-channel sonos memory cell'2004 6,721,204'Memory erase method and device with optimal data retention for nonvolatile memory'2004 6,713,821'Structure of a mask ROM device'2004 6,709,921'Fabrication method for a flash memory device with a split floating gate and a structure thereof'2004 6,706,575'Method for fabricating a non-volatile memory'2004 6,690,601'Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same'2004 6,687,160'Reference current generation circuit for multiple bit flash memory'2004 6,683,352'Semiconductor device structure'2004 6,671,209'Erasing method for p-channel NROM'2003 6,665,212'Reference current generating circuit of multiple bit flash memory'2003 6,661,273'Substrate pump circuit and method for I/O ESD protection'2003 6,657,894'Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells'2003 6,649,971'Nitride read-only memory cell for improving second-bit effect and method for making thereof'2003 6,646,924'Non-volatile memory and operating method thereof'2003 6,643,176'Reference current generation circuit for multiple bit flash memory'2003 6,635,946'Semiconductor device with trench isolation structure'2003 6,628,488'Electrostatic discharge protection circuit'2003 6,624,737'Voltage regulated circuit with well resistor divider'2003 6,620,693'Non-volatile memory and fabrication thereof'2003 6,618,230'Electrostatic discharge cell of integrated circuit'2003 6,613,595'Test structure and method for flash memory tunnel oxide quality'2003 6,614,694'Erase scheme for non-volatile memory'2003 6,607,957'Method for fabricating nitride read only memory'2003 6,590,266'2-bit mask ROM device and fabrication method thereof'2003 6,590,261'Electrostatic discharge protection structure'2003 6,587,387'Device and method for testing mask ROM for bitline to bitline isolation leakage'2003 6,555,844'Semiconductor device with minimal short-channel effects and low bit-line resistance'2003 6,549,029'Circuit and method for measuring capacitance'2003 6,531,361'Fabrication method for a memory device'2003 6,524,919'Method for manufacturing a metal oxide semiconductor with a sharp corner spacer'2003 6,525,361'Process and integrated circuit for a multilevel memory cell with an asymmetric drain'2003 6,524,913'Method of fabricating a non-volatile memory with a spacer'2003 6,514,807'Method for fabricating semiconductor device applied system on chip'2003 6,512,696'Method of programming and erasing a SNNNS type non-volatile memory cell'2003 6,498,377'SONOS component having high dielectric property'2002 6,492,235'Method for forming extension by using double etch spacer'2002 6,482,706'Method to scale down device dimension using spacer to confine buried drain implant'2002 6,482,709'Manufacturing process of a MOS transistor'2002 6,465,849'CMOS structure having dynamic threshold voltage'2002 6,458,643'Method of fabricating a MOS device with an ultra-shallow junction'2002 6,458,642'Method of fabricating a sonos device'2002 6,455,898'Electrostatic discharge input protection for reducing input resistance'2002 6,455,388'Method of manufacturing metal-oxide semiconductor transistor'2002 6,455,376'Method of fabricating flash memory with shallow and deep junctions'2002 6,448,142'Method for fabricating a metal oxide semiconductor transistor'2002 6,444,523'Method for fabricating a memory device with a floating gate'2002 6,432,782'8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate'2002 6,410,963'Electrostatic discharge protection circuits with latch-up prevention function'2002 6,320,786'Method of controlling multi-state NROM'2001 6,269,017'Multi level mask ROM with single current path'2001 6,259,140'Silicide blocking process to form non-silicided regions on MOS devices'2001 6,215,697'Multi-level memory cell device and method for self-converged programming'2001 6,204,529'8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate'2001 6,181,604'Method for fast programming of EPROMS and multi-level flash EPROMS'2001 6,175,519'Virtual ground EPROM structure'2001 6,140,682'Self protected stacked NMOS with non-silicided region to protect mixed-voltage I/O pad from ESD damage'2000 6,121,092'Silicide blocking process to form non-silicided regions on MOS devices'2000 6,046,482'Cell structure for mask ROM'2000 5,963,808'Method of forming an asymmetric bird\'s beak cell for a flash EEPROM'1999 5,895,241'Method for fabricating a cell structure for mask ROM'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2017Patents assigned to MACRONIX INT CO LTD (142)· patent assignee history

1999–2015Based in Kaohsiung, TW· patent location history

2001–2012Based in Koashiung, TW· patent location history

2002–2006Based in Kaoshiung, TW· patent location history

2005–2017Based in Hsinchu, TW· patent location history

2011–2015Patents assigned to LU TAO-CHENG (16)· patent assignee history

2011–2015Patents assigned to CHANG YAO-WEN (10)· patent assignee history

2011–2015Patents assigned to WU GUAN-WEI (6)· patent assignee history

2012–2015Patents assigned to WANG SHIH-YU (6)· patent assignee history

2021Based in Carmel, IN, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MACRONIX INT CO LTD	142	1999–2017
LU TAO-CHENGself	16	2011–2015
CHANG YAO-WEN	10	2011–2015
WANG SHIH-YU	6	2012–2015
WU GUAN-WEI	6	2011–2015

Locations

Location	Patents	Span
Kaohsiung, TW	50	1999–2015
Hsinchu, TW	43	2005–2017
Kaoshiung, TW	40	2002–2006
Koashiung, TW	8	2001–2012
Carmel, IN, US	1	2021