Inventor
Fang Wen Tsai
Inventor
Hsinchu, TW
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1028%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H01LSemiconductor devices25%
H10DInorganic electric semiconductor devices7%
B65GTransport or storage devices, e.g. conveyors for loading or tipping, shop conveyor systems or pneumatic tube conveyors3%
C23CCoating metallic material3%
Y10TTechnical subjects covered by former us classification3%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
PatentTitleYear
10,910,267Alignment marks in substrate having through-substrate via (TSV)202110,692,764Alignment marks in substrate having through-substrate via (TSV)202010,163,706Alignment marks in substrate having through-substrate via (TSV)20189,997,497Through silicon via structure20189,633,900'Method for through silicon via structure'20179,478,480'Alignment mark and method of formation'20169,299,676'Through silicon via structure'20169,099,515'Reconfigurable guide pin design for centering wafers having different sizes'20159,093,314'Copper bump structures having sidewall protection layers'20158,980,706'Double treatment on hard mask for gate N/P patterning'20158,952,506'Through silicon via structure'20158,928,159'Alignment marks in substrate having through-substrate via (TSV)'20158,922,004'Copper bump structures having sidewall protection layers'20148,900,994'Method for producing a protective structure'20148,896,136'Alignment mark and method of formation'20148,691,706'Reducing substrate warpage in semiconductor processing'20148,567,837'Reconfigurable guide pin design for centering wafers having different sizes'20138,513,107'Replacement gate FinFET devices and methods for forming the same'20138,048,810'Method for metal gate N/P patterning'2011RE042514'Extreme low-K dielectric film scheme for advanced interconnects'20117,732,344'High selectivity etching process for metal gate N/P patterning'20107,626,245'Extreme low-k dielectric film scheme for advanced interconnect'20097,465,676'Method for forming dielectric film to improve adhesion of low-k film'20086,953,608'Solution for FSG induced metal corrosion & metal peeling defects with extra bias liner and smooth RF bias ramp up'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (17)· patent assignee history
2005–2021Based in Hsinchu, TW· patent location history
2013–2015Patents assigned to TSAI FANG WEN (8)· patent assignee history
2013–2015Patents assigned to CHIOU WEN-CHIH (6)· patent assignee history
2013–2015Patents assigned to JENG SHIN-PUU (4)· patent assignee history
2016–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 17 | 2005–2016 |
| TSAI FANG WENself | 8 | 2013–2015 |
| CHIOU WEN-CHIH | 6 | 2013–2015 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 6 | 2016–2021 |
| JENG SHIN-PUU | 4 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 24 | 2005–2021 |