Inventor

John M. Cohn

Inventor

Richmond, VT, US

Overview

1996–2021

Patent span

Physics

Primary field (CPC G)

Patents· 75 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing38%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

G01RMeasuring electric variables9%

H10DInorganic electric semiconductor devices5%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%

H04LTransmission of digital information, e.g. telegraphic communication4%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%

G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%

G05BControl or regulating systems in general2%

PatentTitleYear

11,062,323Managing component ownership information across a corresponding life cycle2021 10,489,455Scoped search engine2019 10,446,421Crystal oscillator and the use thereof in semiconductor fabrication2019 10,372,767Sensor based context augmentation of search queries2019 10,275,519Sensor based context augmentation of search queries2019 10,254,725Utilizing automated lighting system to determine occupancy2019 10,257,270Autonomous decentralized peer-to-peer telemetry2019 10,079,881Device self-servicing in an autonomous decentralized peer-to-peer environment2018 9,971,341Crystal oscillator and the use thereof in semiconductor fabrication2018 9,332,362'Acoustic diagnosis and correction system'2016 9,172,718'Endpoint load rebalancing controller'2015 9,160,763'Endpoint load rebalancing controller'2015 9,087,168'Optimizing operating range of an electronic circuit'2015 8,964,995'Acoustic diagnosis and correction system'2015 8,565,510'Methods for reading a feature pattern from a packaged die'2013 8,473,885'Physical design system and method'2013 8,423,328'Method of distributing a random variable using statistically correct spatial interpolation continuously with spatially inhomogeneous statistical correlation versus distance, standard deviation, and mean'2013 8,299,609'Product chips and die with a feature pattern that contains information relating to the product chip'2012 8,230,378'Method for IC wiring yield optimization, including wire widening during and after routing'2012 8,219,943'Physical design system and method'2012 8,187,897'Fabricating product chips and die with a feature pattern that contains information relating to the product chip'2012 7,961,932'Method and apparatus for manufacturing diamond shaped chips'2011 7,895,545'Methods for designing a product chip a priori for design subsetting, feature analysis, and yield learning'2011 7,669,170'Circuit layout methodology using via shape process'2010 7,669,159'IC tiling pattern method, IC so formed and analysis method'2010 7,657,859'Method for IC wiring yield optimization, including wire widening during and after routing'2010 7,644,327'System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA'2010 7,620,931'Method of adding fabrication monitors to integrated circuit chips'2009 7,558,999'Learning based logic diagnosis'2009 7,536,664'Physical design system and method'2009 7,503,021'Integrated circuit diagnosing method, system, and program product'2009 7,469,395'Wiring optimizations for power'2008 7,373,567'System and method of providing error detection and correction capability in an integrated circuit using redundant logic cells of an embedded FPGA'2008 7,346,875'Wiring optimizations for power'2008 7,323,278'Method of adding fabrication monitors to integrated circuit chips'2008 7,308,669'Use of redundant routes to increase the yield and reliability of a VLSI layout'2007 7,289,659'Method and apparatus for manufacturing diamond shaped chips'2007 7,285,860'Method and structure for defect monitoring of semiconductor devices using power bus wiring grids'2007 7,239,167'Utilizing clock shield as defect monitor'2007 7,240,322'Method of adding fabrication monitors to integrated circuit chips'2007 7,222,248'Method of switching voltage islands in integrated circuits when a grid voltage at a reference location is within a specified range'2007 7,194,706'Designing scan chains with specific parameter sensitivities to identify process defects'2007 7,188,322'Circuit layout methodology using a shape processing application'2007 7,135,907'Clock signal distribution utilizing differential sinusoidal signal pair'2006 7,107,469'Power down processing islands'2006 7,095,063'Multiple supply gate array backfill structure'2006 7,093,213'Method for designing an integrated circuit defect monitor'2006 7,089,514'Defect diagnosis for semiconductor integrated circuits'2006 7,088,124'Utilizing clock shield as defect monitor'2006 7,078,248'Method and structure for defect monitoring of semiconductor devices using power bus wiring grids'2006 7,071,757'Clock signal distribution utilizing differential sinusoidal signal pair'2006 7,005,874'Utilizing clock shield as defect monitor'2006 6,998,866'Circuit and method for monitoring defects'2006 6,985,004'Wiring optimizations for power'2006 6,948,146'Simplified tiling pattern method'2005 6,924,661'Power switch circuit sizing technique'2005 6,832,361'System and method for analyzing power distribution using static timing analysis'2004 6,825,711'Power reduction by stage in integrated circuit'2004 6,792,582'Concurrent logical and physical construction of voltage islands for mixed supply voltage designs'2004 6,751,744'Method of integrated circuit design checking using progressive individual network analysis'2004 6,711,719'Method and apparatus for reducing power consumption in VLSI circuit designs'2004 6,687,883'System and method for inserting leakage reduction control in logic circuits'2004 6,651,230'Method for reducing design effect of wearout mechanisms on signal skew in integrated circuit design'2003 6,574,779'Hierarchical layout method for integrated circuits'2003 6,523,159'Method for adding decoupling capacitance during integrated circuit design'2003 6,523,154'Method for supply voltage drop analysis during placement phase of chip design'2003 6,490,708'Method of integrated circuit design by selection of noise tolerant gates'2002 6,479,974'Stacked voltage rails for low-voltage DC distribution'2002 6,473,881'Pattern-matching for transistor level netlists'2002 6,429,469'Optical Proximity Correction Structures Having Decoupling Capacitors'2002 6,430,733'Contextual based groundrule compensation method of mask data set generation'2002 6,189,132'Design rule correction system and method'2001 5,757,657'Adaptive incremental placement of circuits on VLSI chip'1998 5,745,735'Localized simulated annealing'1998 5,535,134'Object placement aid'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to IBM (74)· patent assignee history

1996–2021Based in Richmond, VT, US· patent location history

1998Based in Chittenden County, VT, US· patent location history

2004–2019Based in Essex Junction, VT, US· patent location history

2012–2016Patents assigned to COHN JOHN M (9)· patent assignee history

2012–2013Patents assigned to FINKLER ULRICH A (3)· patent assignee history

2012–2013Patents assigned to FLEMMING MARK J (3)· patent assignee history

2012–2013Patents assigned to HENG FOOK-LUEN (3)· patent assignee history

2012–2013Based in Richland, VT, US· patent location history

2019Based in Burlington, VT, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	74	1996–2021
COHN JOHN Mself	9	2012–2016
FINKLER ULRICH A	3	2012–2013
FLEMMING MARK J	3	2012–2013
HENG FOOK-LUEN	3	2012–2013

Locations

Location	Patents	Span
Richmond, VT, US	67	1996–2021
Essex Junction, VT, US	4	2004–2019
Richland, VT, US	2	2012–2013
Burlington, VT, US	1	2019
Chittenden County, VT, US	1	1998