Inventor
Bryan E. Veal
Inventor
Beaverton, OR, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing53%
H04LTransmission of digital information, e.g. telegraphic communication22%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications9%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%
G06TImage data processing or generation, in general3%
G11CStatic stores3%
PatentTitleYear
10,819,638Reducing network latency during low power operation202010,635,598Memory-addressed maps for persistent storage device20209,910,786'Efficient redundant array of independent disks (RAID) write hole solutions'20189,876,720Reducing network latency during low power operation20189,710,408'Source core interrupt steering'20179,645,739'Host-managed non-volatile memory'20179,569,141'Hash map support in a storage device'20179,471,448'Performing an atomic write operation across multiple storage devices'20169,460,040'Method, device and system for aggregation of shared address devices'20169,317,892'Method and device to augment volatile memory in a graphics subsystem with non-volatile memory'20169,292,213'Maintaining at least one journal and/or at least one data structure by circuitry'20169,054,987'Single instruction processing of network packets'20158,984,309'Reducing network latency during low power operation'20158,938,641'Method and apparatus for synchronizing storage volumes'20158,626,955'Directing packets to a processor unit'20148,493,979'Single instruction processing of network packets'20138,321,615'Source core interrupt steering'20127,836,195'Preserving packet order when migrating network flows between cores'20107,650,488'Communication between processor core partitions with exclusive read or write to descriptor queues for shared memory space'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2020Patents assigned to INTEL CORP (19)· patent assignee history
2010–2015Based in Hillsboro, OR, US· patent location history
2012–2016Patents assigned to VEAL BRYAN E (5)· patent assignee history
2012–2016Patents assigned to FOONG ANNIE (3)· patent assignee history
2012–2020Based in Beaverton, OR, US· patent location history
2013–2016Patents assigned to SCHLUESSLER TRAVIS T (3)· patent assignee history
2015Patents assigned to LAKE DANIEL S (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 19 | 2010–2020 |
| VEAL BRYAN Eself | 5 | 2012–2016 |
| FOONG ANNIE | 3 | 2012–2016 |
| SCHLUESSLER TRAVIS T | 3 | 2013–2016 |
| LAKE DANIEL S | 1 | 2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Beaverton, OR, US | 13 | 2012–2020 |
| Hillsboro, OR, US | 6 | 2010–2015 |