Inventor

Paul S. Zagar

Inventor

Boise, ID, US

Overview

1992–2003

Patent span

Physics

Primary field (CPC G)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary

G11CStatic stores62%

G06FElectric digital data processing15%

H03KPulse technique9%

G01RMeasuring electric variables6%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%

G05BControl or regulating systems in general1%

G05FSystems for regulating electric or magnetic variables1%

PatentTitleYear

6,597,054'Reduced pitch laser redundancy fuse bank structure'2003 6,529,426'Circuit and method for varying a period of an internal control signal during a test mode'2003 6,208,568'Circuit for cancelling and replacing redundant elements'2001 6,201,740'Cache memories using DRAM cells with high-speed data path'2001 RE036952'One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture'2000 6,104,645'High speed global row redundancy system'2000 RE036821'Wordline driver circuit having a directly gated pull-down device'2000 6,097,647'Efficient method for obtaining usable parts from a partially good memory integrated circuit'2000 6,044,433'DRAM cache'2000 5,999,480'Dynamic random-access memory having a hierarchical data path'1999 5,991,214'Circuit and method for varying a period of an internal control signal during a test mode'1999 5,970,008'Efficient method for obtaining usable parts from a partially good memory integrated circuit'1999 5,953,739'Synchronous DRAM cache using write signal to determine single or burst write'1999 5,933,372'Data path for high speed high bandwidth DRAM'1999 5,912,579'Circuit for cancelling and replacing redundant elements'1999 5,905,295'Reduced pitch laser redundancy fuse bank structure'1999 5,901,105'Dynamic random access memory having decoding circuitry for partial memory blocks'1999 5,850,368'Burst EDO memory address counter'1998 5,844,833'DRAM with open digit lines and array edge reference sensing'1998 5,838,620'Circuit for cancelling and replacing redundant elements'1998 5,831,918'Circuit and method for varying a period of an internal control signal during a test mode'1998 5,812,488'Synchronous burst extended data out dram'1998 5,801,996'Data path for high speed high bandwidth DRAM'1998 5,802,010'Burst EDO memory device'1998 5,774,412'Local word line phase driver'1998 RE035825'Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts'1998 5,761,145'Efficient method for obtaining usable parts from a partially good memory integrated circuit'1998 5,747,869'Reduced pitch laser redundancy fuse bank structure'1998 RE035750'Wordline driver circuit having an automatic precharge circuit'1998 5,726,931'DRAM with open digit lines and array edge reference sensing'1998 5,696,732'Burst EDO memory device'1997 5,677,884'Circuit for cancelling and replacing redundant elements'1997 5,675,549'Burst EDO memory device address counter'1997 5,668,773'Synchronous burst extended data out DRAM'1997 5,666,323'Synchronous NAND DRAM architecture'1997 5,661,695'Burst EDO memory device'1997 5,636,172'Reduced pitch laser redundancy fuse bank structure'1997 5,608,668'Dram wtih open digit lines and array edge reference sensing'1997 5,587,671'Semiconductor device having an output buffer which reduces signal degradation due to leakage of current'1996 5,586,080'Local word line phase driver'1996 5,552,739'Integrated circuit power supply having piecewise linearity'1996 5,544,124'Optimization circuitry and control for a synchronous memory device with programmable latency period'1996 5,528,539'High speed global row redundancy system'1996 5,526,320'Burst EDO memory device'1996 5,513,148'Synchronous NAND DRAM architecture'1996 5,488,583'Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits'1996 5,465,232'Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory'1995 5,384,500'Programmable logic device macrocell with an exclusive feedback and an exclusive external input line for a combinatorial mode and accommodating two separate programmable or planes'1995 5,325,331'Improved device for sensing information store in a dynamic memory'1994 5,315,177'One time programmable fully-testable programmable logic device with zero power and anti-fuse cell architecture'1994 5,311,481'Wordline driver circuit having a directly gated pull-down device'1994 5,311,478'Integrated circuit memory with asymmetric row access topology'1994 5,293,342'Wordline driver circuit having an automatic precharge circuit'1994 5,287,017'Programmable logic device macrocell with two OR array inputs'1994 5,285,408'Method and apparatus for providing a faster ones voltage level restore operation in a dram'1994 5,270,587'CMOS logic cell for high-speed, zero-power programmable array logic devices'1993 5,235,550'Method for maintaining optimum biasing voltage and standby current levels in a DRAM array having repaired row-to-column shorts'1993 5,235,221'Field programmable logic array with speed optimized architecture'1993 5,220,215'Field programmable logic array with two or planes'1993 5,148,391'Nonvolatile, zero-power memory cell constructed with capacitor-like antifuses operable at less than power supply voltage'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2003Patents assigned to MICRON TECHNOLOGY INC (52)· patent assignee history

1992–2003Based in Boise, ID, US· patent location history

1994–1996Patents assigned to MICRON SEMICONDUCTOR INC (5)· patent assignee history

1994Patents assigned to CASPER STEPHEN L (1)· patent assignee history

1994Patents assigned to ONG ADRIAN (1)· patent assignee history

1994Patents assigned to ZAGAR PAUL S (1)· patent assignee history

1998–2000Based in Woodinville, WA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	52	1992–2003
MICRON SEMICONDUCTOR INC	5	1994–1996
CASPER STEPHEN L	1	1994
ONG ADRIAN	1	1994
ZAGAR PAUL Sself	1	1994

Locations

Location	Patents	Span
Boise, ID, US	57	1992–2003
Woodinville, Washington, US	3	1998–2000