Inventor
Hsin-Hui Lee
Inventor
Kaohsiung, TW
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1011%
H10DInorganic electric semiconductor devices7%
H01LSemiconductor devices6%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation6%
H05KPrinted circuits4%
Y10TTechnical subjects covered by former us classification4%
G02BOptical elements, systems or apparatus3%
B28DWorking stone or stone-like materials2%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices2%
PatentTitleYear
10,770,602Optical sensor and method for forming the same202010,763,288Semiconductor device and method for forming the same202010,699,092Optical sensor and manufacturing method thereof202010,651,218Optical sensor structure and method for forming the same202010,572,070Optical devices and fabrication method thereof20209,904,302'Proactive pressure stabilizing system and method'20189,812,409'Seal ring structure with a metal pad'20179,064,817'Structure of wafer level chip molded package'20159,035,445'Seal ring structure with a metal pad'20158,647,963'Structure and method of wafer level chip molded packaging'20148,524,595'Semiconductor package structures'20138,497,584'Method to improve bump reliability for flip chip device'20138,409,881'Multi-project wafer and method of making same'20138,288,842'Method for dicing semiconductor wafers'20128,283,754'Seal ring structure with metal pad'20128,039,315'Thermally enhanced wafer level package'20117,952,167'Scribe line layout design'20117,906,425'Fluxless bumping process'20117,851,272'Multi-project wafer and method of making same'20107,851,916'Strain silicon wafer with a crystal orientation (100) in flip chip BGA package'20107,772,691'Thermally enhanced wafer level package'20107,642,631'Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer'20107,491,624'Method of manufacturing low CTE substrates for use with low-k flip-chip package devices'20097,468,321'Application of impressed-current cathodic protection to prevent metal corrosion and oxidation'20087,361,990'Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads'20087,294,937'Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling'20077,276,454'Application of impressed-current cathodic protection to prevent metal corrosion and oxidation'20077,265,034'Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade'20077,256,071'Underfilling efficiency by modifying the substrate design of flip chips'20077,183,137'Method for dicing semiconductor wafers'20077,170,159'Low CTE substrates for use with low-k flip-chip package devices'20077,154,185'Encapsulation method for SBGA'20067,148,560'IC chip package structure and underfill process'20067,134,199'Fluxless bumping process'20067,126,225'Apparatus and method for manufacturing a semiconductor wafer with reduced delamination and peeling'20067,112,882'Structures and methods for heat dissipation of semiconductor integrated circuits'20067,098,082'Microelectronics package assembly tool and method of manufacture therewith'20067,075,016'Underfilling efficiency by modifying the substrate design of flip chips'20066,974,659'Method of forming a solder ball using a thermally stable resinous protective layer'20056,805,279'Fluxless bumping process using ions'20046,802,250'Stencil design for solder paste printing'20046,797,075'Ferris wheel-like stripping or cleaning mechanism for semiconductor fabrication'20046,756,294'Method for improving bump reliability for flip chip devices'20046,743,660'Method of making a wafer level chip scale package'20046,715,524'DFR laminating and film removing system'20046,636,313'Method of measuring photoresist and bump misalignment'20036,602,775'Method to improve reliability for flip-chip device for limiting pad design'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2015Patents assigned to TAIWAN SEMICONDUCTOR MFG (40)· patent assignee history
2003–2006Based in Hsinchu, TW· patent location history
2004–2020Based in Kaohsiung, TW· patent location history
2006–2007Based in Koahsiung, TW· patent location history
2011Based in Kaoshiugh, TW· patent location history
2012–2014Patents assigned to LEE HSIN-HUI (6)· patent assignee history
2013–2014Patents assigned to CHENG WILLIAM (2)· patent assignee history
2013Patents assigned to LII MIRNG-JI (2)· patent assignee history
2018Based in Keelung, TW· patent location history
2020Patents assigned to VANGUARD INT SEMICONDUCT CORP (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 40 | 2003–2015 |
| LEE HSIN-HUIself | 6 | 2012–2014 |
| VANGUARD INT SEMICONDUCT CORP | 5 | 2020 |
| CHENG WILLIAM | 2 | 2013–2014 |
| LII MIRNG-JI | 2 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kaohsiung, TW | 37 | 2004–2020 |
| Hsinchu, TW | 3 | 2003–2006 |
| Koahsiung, TW | 2 | 2006–2007 |
| Keelung, TW | 1 | 2018 |
| Kaoshiugh, TW | 1 | 2011 |