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Inventor

Yupin Fong

Inventor
Fremont, CA, US

Overview

103→
Patents
1993–2017
Patent span
Physics
Primary field (CPC G)

Patents· 103 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores51%
H10BElectronic memory devices26%
H10DInorganic electric semiconductor devices21%
G06FElectric digital data processing2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%
PatentTitleYear
RE046264'Verification process for non-volatile storage'2017RE045544'Saw-shaped multi-pulse programming for program noise reduction in memory'2015RE045515'Built in on-chip data scrambler for non-volatile memory'20158,570,810'Intelligent control of program pulse for non-volatile storage'20138,546,239'Methods of fabricating non-volatile memory with air gaps'20138,429,330'Method for scrambling data in which scrambling data and scrambled data are stored in corresponding non-volatile memory locations'20138,288,225'Method of reducing coupling between floating gates in nonvolatile memory'20128,228,741'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20128,218,367'Verification process for non-volatile storage'2012RE043417'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20128,145,855'Built in on-chip data scrambler for non-volatile memory'20128,116,140'Saw-shaped multi-pulse programming for program noise reduction in memory'20127,978,527'Verification process for non-volatile storage'20117,969,778'System that compensates for coupling based on sensing a neighbor using coupling'20117,910,434'Method of reducing coupling between floating gates in nonvolatile memory'20117,898,868'Multi-state memory'20117,894,273'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20117,885,112'Nonvolatile memory and method for on-chip pseudo-randomization of data within a page and between pages'20117,858,472'Scalable self-aligned dual floating gate memory cell array and methods of forming the array'20107,768,836'Nonvolatile memory and method with reduced program verify by ignoring fastest and/or slowest programming bits'20107,734,861'Pseudo random and command driven bit compensation for the cycling effects in flash memory'20107,630,249'Intelligent control of program pulse duration'20097,615,445'Methods of reducing coupling between floating gates in nonvolatile memory'20097,616,480'System that compensates for coupling based on sensing a neighbor using coupling'20097,606,966'Methods in a pseudo random and command driven bit compensation for the cycling effects in flash memory'20097,602,647'System that compensates for coupling based on sensing a neighbor using coupling'20097,584,391'Smart verify for multi-state memories'20097,580,290'Non-volatile storage system with intelligent control of program pulse duration'20097,573,740'Multi-state memory'20097,522,454'Compensating for coupling based on sensing a neighbor using coupling'20097,518,928'Efficient verification for coarse/fine programming of non volatile memory'20097,495,956'Reducing read disturb for non-volatile storage'20097,457,162'Multi-state memory'20087,453,735'Non-volatile memory and control with improved partial page program capability'20087,453,730'Charge packet metering for coarse/fine programming of non-volatile memory'20087,449,746'EEPROM with split gate source side injection'20087,447,065'Reducing read disturb for non-volatile storage'20087,447,075'Charge packet metering for coarse/fine programming of non-volatile memory'20087,443,729'System that compensates for coupling based on sensing a neighbor using coupling'20087,443,723'Multi-state memory'20087,440,318'Reducing read disturb for non-volatile storage'20087,414,887'Variable current sinking for coarse/fine programming of non-volatile memory'20087,411,827'Boosting to control programming of non-volatile memory'20087,397,698'Reducing floating gate to floating gate coupling effect'20087,385,843'Multi-state memory'20087,349,258'Reducing read disturb for non-volatile storage'20087,345,934'Multi-state memory'20087,317,638'Efficient verification for coarse/fine programming of non-volatile memory'20087,301,812'Boosting to control programming of non-volatile memory'20077,295,473'System for reducing read disturb for non-volatile storage'20077,289,360'Multi-state memory'20077,280,408'Bitline governed approach for programming non-volatile memory'20077,280,396'Non-volatile memory and control with improved partial page program capability'20077,262,994'System for reducing read disturb for non-volatile storage'20077,243,275'Smart verify for multi-state memories'20077,230,851'Reducing floating gate to floating gate coupling effect'20077,224,613'Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states'20077,211,866'Scalable self-aligned dual floating gate memory cell array and methods of forming the array'20077,187,592'Multi-state memory'20077,170,786'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20077,139,198'Efficient verification for coarse/fine programming of non-volatile memory'20067,088,615'Multi-state memory'20067,088,621'Bitline governed approach for coarse/fine programming'20067,073,103'Smart verify for multi-state memories'20067,071,060'EEPROM with split gate source side infection with sidewall spacers'20067,068,539'Charge packet metering for coarse/fine programming of non-volatile memory'20067,061,798'Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states'20067,057,939'Non-volatile memory and control with improved partial page program capability'20067,046,548'Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells'20067,035,146'Programming non-volatile memory'20067,023,733'Boosting to control programming of non-volatile memory'20067,020,026'Bitline governed approach for program control of non-volatile memory'20067,002,843'Variable current sinking for coarse/fine programming of non-volatile memory'20066,953,970'Scalable self-aligned dual floating gate memory cell array and methods of forming the array'20056,954,381'EEPROM with split gate source side injection with sidewall spacers'20056,898,121'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20056,894,926'Multi-state memory'20056,894,930'Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND'20056,888,758'Programming non-volatile memory'20056,870,768'Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells'20056,861,700'Eeprom with split gate source side injection'20056,862,218'Multi-state memory'20056,856,546'Multi-state memory'20056,807,095'Multi-state nonvolatile memory capable of reducing effects of coupling between storage elements'20046,781,877'Techniques for reducing effects of coupling between storage elements of adjacent rows of memory cells'20046,762,092'Scalable self-aligned dual floating gate memory cell array and methods of forming the array'20046,704,222'Multi-state operation of dual floating gate array'20046,664,587'EEPROM cell array structure with specific floating gate shape'20036,522,580'Operating techniques for reducing effects of coupling between storage elements of a non-volatile memory operated in multiple data states'20036,317,363'Multi-state memory'20016,317,364'Multi-state memory'20016,275,419'Multi-state memory'20016,222,762'Multi-state memory'20016,002,152'EEPROM with split gate source side injection with sidewall spacers'19995,910,925'EEPROM with split gate source side injection'19995,910,915'EEPROM with split gate source side injection'19995,883,409'EEPROM with split gate source side injection'19995,867,429'High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates'19995,847,996'Eeprom with split gate source side injection'19985,776,810'Method for forming EEPROM with split gate source side injection'19985,712,180'EEPROM with split gate source side injection'19985,313,421'EEPROM with split gate source side injection'19945,272,669'Method and structure for programming floating gate memory cells'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2017Based in Fremont, CA, US· patent location history
1998–2011Patents assigned to SANDISK CORP (85)· patent assignee history
2009Based in Milpitas, CA, US· patent location history
2011–2017Patents assigned to SANDISK TECHNOLOGIES INC (13)· patent assignee history
2012–2013Patents assigned to FONG YUPIN (4)· patent assignee history
2012–2013Patents assigned to WAN JUN (4)· patent assignee history
2012–2013Patents assigned to FONG YUPIN K (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SANDISK CORP851998–2011
SANDISK TECHNOLOGIES INC132011–2017
FONG YUPINself42012–2013
WAN JUN42012–2013
FONG YUPIN Kself32012–2013
Locations
LocationPatentsSpan
Fremont, California, US1021993–2017
Milpitas, California, US12009