Inventor

Jeong Soo Byun

Inventor

Cupertino, CA, US

Overview

1995–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Pprimary

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1027%

C23CCoating metallic material19%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

H10DInorganic electric semiconductor devices17%

C30BSingle-crystal growth5%

B82YSpecific uses or applications of nanostructures4%

H01LSemiconductor devices4%

H10BElectronic memory devices3%

H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%

PatentTitleYear

10,908,513Metrology method and apparatus and computer program2021 10,593,812Radical oxidation process for fabricating a nonvolatile charge trap memory device2020 10,319,733Oxide formation in a plasma process2019 10,304,968Radical oxidation process for fabricating a nonvolatile charge trap memory device2019 10,269,985Radical oxidation process for fabricating a nonvolatile charge trap memory device2019 10,128,258Oxide formation in a plasma process2018 10,090,416Radical oxidation process for fabricating a nonvolatile charge trap memory device2018 9,460,974'Oxide formation in a plasma process'2016 9,406,574'Oxide formation in a plasma process'2016 9,031,685'Atomic layer deposition apparatus'2015 8,993,453'Method of fabricating a nonvolatile charge trap memory device'2015 8,940,645'Radical oxidation process for fabricating a nonvolatile charge trap memory device'2015 8,822,349'Oxide formation in a plasma process'2014 8,691,648'Methods for fabricating semiconductor memory with process induced strain'2014 8,626,330'Atomic layer deposition apparatus'2014 8,592,891'Methods for fabricating semiconductor memory with process induced strain'2013 8,318,608'Method of fabricating a nonvolatile charge trap memory device'2012 8,168,933'Method for forming image sensor with shield structures'2012 8,119,538'Oxide formation in a plasma process'2012 8,110,787'Image sensor with a reflective waveguide'2012 8,027,746'Atomic layer deposition apparatus'2011 7,860,597'Atomic layer deposition apparatus'2010 7,846,840'Method for forming tungsten materials during vapor deposition processes'2010 7,799,670'Plasma oxidation of a memory layer to form a blocking layer in non-volatile charge trap memory devices'2010 7,749,815'Methods for depositing tungsten after surface treatment'2010 7,745,333'Methods for depositing tungsten layers employing atomic layer deposition techniques'2010 7,674,715'Method for forming tungsten materials during vapor deposition processes'2010 7,660,644'Atomic layer deposition apparatus'2010 7,605,083'Formation of composite tungsten films'2009 7,501,344'Formation of boride barrier layers using chemisorption techniques'2009 7,501,343'Formation of boride barrier layers using chemisorption techniques'2009 7,485,556'Forming metal silicide on silicon-containing features of a substrate'2009 7,465,666'Method for forming tungsten materials during vapor deposition processes'2008 7,405,158'Methods for depositing tungsten layers employing atomic layer deposition techniques'2008 7,384,867'Formation of composite tungsten films'2008 7,294,588'In-situ-etch-assisted HDP deposition'2007 7,238,552'Method and apparatus for depositing tungsten after surface treatment to improve film characteristics'2007 7,235,486'Method for forming tungsten materials during vapor deposition processes'2007 7,208,413'Formation of boride barrier layers using chemisorption techniques'2007 7,115,494'Method and system for controlling the presence of fluorine in refractory metal layers'2006 7,085,616'Atomic layer deposition apparatus'2006 7,049,211'In-situ-etch-assisted HDP deposition using SiF4'2006 7,033,922'Method and system for controlling the presence of fluorine in refractory metal layers'2006 7,033,945'Gap filling with a composite layer'2006 6,939,804'Formation of composite tungsten films'2005 6,936,538'Method and apparatus for depositing tungsten after surface treatment to improve film characteristics'2005 6,903,031'In-situ-etch-assisted HDP deposition using SiF4 and hydrogen'2005 6,855,368'Method and system for controlling the presence of fluorine in refractory metal layers'2005 6,849,545'System and method to form a composite film stack utilizing sequential deposition techniques'2005 6,831,004'Formation of boride barrier layers using chemisorption techniques'2004 6,620,723'Formation of boride barrier layers using chemisorption techniques'2003 6,551,929'Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques'2003 6,221,762'Method for fabricating semiconductor device having improved step coverage and low resistivity contacts'2001 6,171,981'Electrode passivation layer of semiconductor device and method for forming the same'2001 6,096,630'Method for fabricating semiconductor device'2000 6,077,750'Method for forming epitaxial Co self-align silicide for semiconductor device'2000 5,824,600'Method for forming a silicide layer in a semiconductor device'1998 5,744,398'Method of forming electrode of semiconductor device'1998 5,712,181'Method for the formation of polycide gate in semiconductor device'1998 5,668,040'Method for forming a semiconductor device electrode which also serves as a diffusion barrier'1997 5,665,209'Method for forming refractory metal nitride film'1997 5,645,887'Method for forming platinum silicide plugs'1997 5,607,884'Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film'1997 5,604,140'Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same'1997 5,599,734'Method for fabricating MOS transistor utilizing doped disposable layer'1997 5,597,745'Method for forming TiN film and TiN film/thin TiSi.sub.2 film, and method for fabricating semiconductor element utilizing the same'1997 5,591,667'Method for fabricating MOS transistor utilizing doped disposable layer'1997 5,413,957'Method for fabricating MOS transistor having source/drain region of shallow junction and silicide film'1995

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1995–2001Based in Chungcheongbuk-do, KR· patent location history

1997–2001Patents assigned to LG SEMICON CO LTD (14)· patent assignee history

1997Based in Chungcheongnam-do, KR· patent location history

1998–2021Based in Seoul, KR· patent location history

2000Based in Cheongju, KR· patent location history

2003–2015Patents assigned to APPLIED MATERIALS INC (33)· patent assignee history

2003–2020Based in Cupertino, CA, US· patent location history

2010–2019Patents assigned to CYPRESS SEMICONDUCTOR CORP (13)· patent assignee history

2012–2015Patents assigned to RAMKUMAR KRISHNASWAMY (7)· patent assignee history

2012–2014Patents assigned to BYUN JEONG SOO (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
APPLIED MATERIALS INC	33	2003–2015
LG SEMICON CO LTD	14	1997–2001
CYPRESS SEMICONDUCTOR CORP	13	2010–2019
RAMKUMAR KRISHNASWAMY	7	2012–2015
BYUN JEONG SOOself	6	2012–2014

Locations

Location	Patents	Span
Cupertino, California, US	51	2003–2020
Chungcheongbuk-do, KR	13	1995–2001
Seoul, KR	2	1998–2021
Cheongju, KR	1	2000
Chungcheongnam-do, KR	1	1997