Inventor

Dennis R. Bradford

Inventor

Portland, OR, US

Overview

20→

Patents

2011–2020

Patent span

Physics

Primary field (CPC G)

Patents· 20 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing65%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use13%

H10DInorganic electric semiconductor devices6%

Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications6%

G05FSystems for regulating electric or magnetic variables3%

G11CStatic stores3%

H03MCoding3%

PatentTitleYear

10,853,065Systems, apparatuses, and methods for chained fused multiply add2020 10,817,291Apparatuses, methods, and systems for swizzle operations in a configurable spatial accelerator2020 10,795,680Vector friendly instruction format and execution thereof2020 10,719,320Power noise injection to control rate of change of current2020 10,678,541Processors having fully-connected interconnects shared by vector conflict instructions and permute instructions2020 10,649,772Method and apparatus for efficient matrix transpose2020 10,423,421Opportunistic utilization of redundant ALU2019 10,268,539Apparatus and method for multi-bit error detection and correction2019 10,146,535Systems, apparatuses, and methods for chained fused multiply add2018 10,133,577Vector mask driven clock gating for power efficiency of a processor2018 9,842,046'Processing memory access instructions that have duplicate memory indices'2017 9,804,842'Method and apparatus for efficiently managing architectural register state of a processor'2017 9,785,436'Apparatus and method for efficient gather and scatter operations'2017 9,696,992'Apparatus and method for performing a check to optimize instruction flow'2017 9,606,847'Enabling error detecting and reporting in machine check architecture'2017 9,513,917'Vector friendly instruction format and execution thereof'2016 9,323,500'Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values'2016 9,152,382'Reducing power consumption in a fused multiply-add (FMA) unit responsive to input data values'2015 8,473,715'Dynamic accelerator reconfiguration via compiler-inserted initialization message and configuration address and size information'2013 8,082,418'Method and apparatus for coherent device initialization and access'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011–2020Patents assigned to INTEL CORP (20)· patent assignee history

2011–2016Patents assigned to BRADFORD DENNIS (3)· patent assignee history

2011–2013Patents assigned to CHITLUR NAGABHUSHAN (2)· patent assignee history

2011–2013Patents assigned to RANKIN LINDA (2)· patent assignee history

2011–2013Patents assigned to STILLWELL JR PAUL M (2)· patent assignee history

2011–2020Based in Portland, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	20	2011–2020
BRADFORD DENNISself	3	2011–2016
CHITLUR NAGABHUSHAN	2	2011–2013
RANKIN LINDA	2	2011–2013
STILLWELL JR PAUL M	2	2011–2013

Locations

Location	Patents	Span
Portland, OR, US	20	2011–2020