LexDanaLexDanabeta
Inventor

Ju Shen

Inventor
San Jose, CA, US

Overview

54→
Patents
1992–2016
Patent span
Electricity
Primary field (CPC H)

Patents· 54 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique75%
G06FElectric digital data processing16%
G01RMeasuring electric variables5%
G11CStatic stores3%
G09BEducational or demonstration appliances2%
PatentTitleYear
9,496,047'Memory cell and memory'20169,183,922'Eight transistor (8T) write assist static random access memory (SRAM) cell'20159,075,826'Image matching'20158,371,856'Game box with replaceable figure boards'20137,895,555'Simultaneous switching output noise estimation and reduction systems and methods'20117,876,125'Register data retention systems and methods during reprogramming of programmable logic devices'20117,834,652'Method and devices for storing a security key using programmable fuses'20107,788,620'Input/output placement systems and methods to reduce simultaneous switching output noise'20107,675,313'Methods and systems for storing a security key using programmable fuses'20107,652,500'Reconfiguration of programmable logic devices'20107,573,291'Programmable logic device with enhanced logic block architecture'20097,535,253'Register data retention systems and methods during reprogramming of programmable logic devices'20097,375,549'Reconfiguration of programmable logic devices'20087,327,160'SERDES with programmable I/O architecture'20087,295,035'Programmable logic device with enhanced logic block architecture'20077,208,975'SERDES with programmable I/O architecture'20076,915,323'Macrocells supporting a carry cascade'20056,903,573'Programmable logic device with enhanced wide input product term cascading'20056,828,823'Non-volatile and reconfigurable programmable logic devices'20046,777,979'FIFO memory architecture'20046,765,408'Device and method with generic logic blocks'20046,567,969'Configurable logic array including lookup table means for generating functions of different numbers of input terms'20036,462,576'Programmable logic device'20026,356,107'Method and structure dynamic in-system programming'20026,304,099'Method and structure for dynamic in-system programming'20016,294,925'Programmable logic device'20016,278,311'Method for minimizing instantaneous currents when driving bus signals'20016,255,847'Programmable logic device'20016,229,336'Programmable integrated circuit device with slew control and skew control'20016,191,609'Combination of global clock and localized clocks'20016,133,750'Combination of global clock and localized clocks'20006,128,770'Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)'20006,104,207'Programmable logic device'20006,066,977'Programmable output voltage levels'20005,740,069'Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs)'19985,598,346'Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks'19975,587,921'Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer'19965,586,044'Array of configurable logic blocks including cascadable lookup tables'19965,490,074'Constant delay interconnect for coupling configurable logic blocks'19965,469,368'Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output'19955,422,823'Programmable gate array device having cascaded means for function definition'19955,412,260'Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device'19955,394,033'Structure and method for implementing hierarchical routing pools in a programmable logic circuit'19955,359,536'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19945,336,951'Structure and method for multiplexing pins for in-system programming'19945,329,460'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19945,260,881'Programmable gate array with improved configurable logic block'19935,237,218'Structure and method for multiplexing pins for in-system programming'19935,233,539'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19935,212,652'Programmable gate array with improved interconnect structure'19935,191,243'Output logic macrocell with enhanced functional capabilities'19935,162,679'Sense amplifier with depletion transistor feedback'19925,138,198'Integrated programmable logic device with control circuit to power down unused sense amplifiers'19925,130,574'Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2011Patents assigned to LATTICE SEMICONDUCTOR CORP (37)· patent assignee history
1992–2011Based in San Jose, CA, US· patent location history
1993–1998Patents assigned to ADVANCED MICRO DEVICES INC (12)· patent assignee history
1995–2005Based in Saratoga, CA, US· patent location history
2001–2002Based in Milpitas, CA, US· patent location history
2015–2016Patents assigned to NVIDIA CORP (2)· patent assignee history
2015Patents assigned to HEWLETT PACKARD DEVELOPMENT CO (1)· patent assignee history
2015–2016Based in Shanghai, CN· patent location history
2015Based in Palo Alto, CA, US· patent location history
2016Patents assigned to CHEN HUA (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LATTICE SEMICONDUCTOR CORP371992–2011
ADVANCED MICRO DEVICES INC121993–1998
NVIDIA CORP22015–2016
CHEN HUA12016
HEWLETT PACKARD DEVELOPMENT CO12015
Locations
LocationPatentsSpan
San Jose, California, US341992–2011
Saratoga, California, US141995–2005
Shanghai, CN22015–2016
Milpitas, California, US22001–2002
Palo Alto, California, US12015