Inventor
MARK A. SCHMISSEUR
Inventor
US
Overview
Patents· 30 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing42%
H04LTransmission of digital information, e.g. telegraphic communication19%
G06NComputing arrangements based on specific computational models16%
C07FAcyclic, carbocyclic or heterocyclic compounds containing elements other than carbon, hydrogen, halogen, oxygen, nitrogen, sulfur, selenium or tellurium5%
G11CStatic stores5%
H04QSelecting3%
H05KPrinted circuits3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
B25JManipulators2%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes2%
PatentTitleYear
12,566,559Managing memory system quality of service (QoS)202612,556,464Techniques to control quality of service for end-to-end paths in a compute environment202612,499,071System decoder for training accelerators202512,422,989Memory schemes for infrastructure processing unit architectures202512,332,740Application aware memory patrol scrubbing techniques202512,314,188Platform data aging for adaptive memory scaling202512,204,471Shared memory for intelligent network interface cards202512,088,507Scalable edge computing202412,038,861System decoder for training accelerators202411,994,997Memory controller to manage quality of service enforcement and migration between local and pooled memory202411,983,408Ballooning for multi-tiered pooled memory202411,907,136Apparatuses, systems, and methods for invalidating expired memory202411,870,662Techniques to control quality of service for end-to-end paths in a compute environment202411,809,338Shared memory for intelligent network interface cards202311,797,343Data management for edge architectures202311,681,439Ballooning for multi-tiered pooled memory202311,586,575System decoder for training accelerators202311,573,722Tenant based allocation for pooled memory202311,456,966Scalable edge computing202211,392,425Technologies for providing a split memory pool for full rack connectivity202211,354,127Method of managing multi-tier memory displacement using software controlled thresholds202211,329,898Techniques to control quality of service for end-to-end paths in a compute environment202211,295,235Filtering training data for models in a data center202211,269,801System decoder for training accelerators202211,263,162System decoder for training accelerators202211,216,396Persistent memory write semantics on PCIe with existing TLP definition202211,200,104Technolgies for millimeter wave rack interconnects202111,178,063Remote hardware acceleration202111,176,091Techniques for dynamic multi-storage format database access202111,157,422Shared memory for intelligent network interface cards2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (30)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 30 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 30 | 2021–2026 |