Inventor
Darren L. Anand
Inventor
Essex Junction, VT, US
Overview
Patents· 46 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores65%
G01RMeasuring electric variables8%
G06FElectric digital data processing6%
H03KPulse technique5%
H01LSemiconductor devices3%
H10BElectronic memory devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H10DInorganic electric semiconductor devices2%
PatentTitleYear
10,826,489Selection circuit202010,685,705Program and erase memory structures202010,535,379Latching current sensing amplifier for memory array202010,468,104Robust and error free physical unclonable function using twin-cell charge trap transistor memory201910,395,752Margin test for multiple-time programmable memory (MTPM) with split wordlines201910,163,526Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing201810,062,445Parallel programming of one time programmable memory array for reduced test time20189,953,727Circuit and method for detecting time dependent dielectric breakdown (TDDB) shorts and signal-margin testing20189,779,783'Latching current sensing amplifier for memory array'20179,508,420'Voltage-aware adaptive static random access memory (SRAM) write assist circuit'20169,281,045'Refresh hidden eDRAM memory'20168,773,920'Reference generator with programmable M and B parameters and methods of use'20148,649,239'Multi-bank random access memory structure with global and local signal buffering for improved performance'20148,484,543'Fusebay controller structure, system, and method'20138,028,195'Structure for indicating status of an on-chip power supply system'20117,984,329'System and method for providing DRAM device-level repair via address remappings external to the device'20117,920,003'Delay circuit with delay equal to percentage of input pulse width'20117,916,826'Diagnostic method and apparatus for non-destructively observing latch data'20117,917,806'System and method for indicating status of an on-chip power supply system'20117,911,820'Regulating electrical fuse programming current'20117,895,028'Structure for increasing fuse programming yield'20117,688,654'Structure for differential eFUSE sensing without reference fuses'20107,609,577'Design structure for improving sensing margin of electrically programmable fuses'20097,525,831'Method for improving sensing margin of electrically programmable fuses'20097,512,915'Embedded test circuit for testing integrated circuits at the die level'20097,477,555'System and method for differential eFUSE sensing without reference fuses'20097,453,973'Diagnostic method and apparatus for non-destructively observing latch data'20087,444,564'Automatic bit fail mapping for embedded memories with clock multipliers'20087,382,149'System for acquiring device parameters'20087,315,193'Circuitry and method for programming an electrically programmable fuse'20087,307,911'Apparatus and method for improving sensing margin of electrically programmable fuses'20077,251,756'Method and apparatus for increasing fuse programming yield through preferred use of duplicate data'20077,243,279'Method for separating shift and scan paths on scan-only, single port LSSD latches'20077,170,299'Electronic fuse blow mimic and methods for adjusting electronic fuse blow'20077,145,977'Diagnostic method and apparatus for non-destructively observing latch data'20067,089,136'Method for reduced electrical fusing time'20067,061,304'Fuse latch with compensated programmable resistive trip point'20066,995,585'System and method for implementing self-timed decoded data paths in integrated circuits'20066,956,415'Modular DLL architecture for generating multiple timings'20056,944,090'Method and circuit for precise timing of signals in an embedded DRAM array'20056,788,591'System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch'20046,768,694'Method of electrically blowing fuses under control of an on-chip tester interface apparatus'20046,728,159'Flexible multibanking interface for embedded memory applications'20046,577,156'Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox'20036,552,938'Column redundancy system and method for embedded DRAM devices with multibanking capability'20035,978,281'Method and apparatus for preventing postamble corruption within a memory system'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2017Patents assigned to IBM (37)· patent assignee history
1999–2011Based in Essex Junction, VT, US· patent location history
2011–2020Based in Williston, VT, US· patent location history
2013–2014Patents assigned to ANAND DARREN L (3)· patent assignee history
2013Patents assigned to GORMAN KEVIN W (1)· patent assignee history
2014Patents assigned to FIFIELD JOHN A (2)· patent assignee history
2016–2020Patents assigned to GLOBALFOUNDRIES INC (10)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 37 | 1999–2017 |
| GLOBALFOUNDRIES INC | 10 | 2016–2020 |
| ANAND DARREN Lself | 3 | 2013–2014 |
| FIFIELD JOHN A | 2 | 2014 |
| GORMAN KEVIN W | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 28 | 1999–2011 |
| Williston, VT, US | 18 | 2011–2020 |