Inventor
Zicheng Gary Ling
Inventor
San Jose, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
G01RMeasuring electric variables30%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1017%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
G06FElectric digital data processing7%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
PatentTitleYear
10,289,784Determination of clock path delays and implementation of a circuit design20197,724,016'Characterizing circuit performance by separating device and interconnect impact on signal delay'20107,489,152'Characterizing circuit performance by separating device and interconnect impact on signal delay'20097,109,734'Characterizing circuit performance by separating device and interconnect impact on signal delay'20067,046,026'Testing vias and contracts in integrated circuit'20066,868,537'Method of generating an IC mask using a reduced database'20056,867,580'Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits'20056,842,019'Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits'20056,784,685'Testing vias and contacts in an integrated circuit'20046,727,710'Structures and methods for determining the effects of high stress currents on conducting layers and contacts in integrated circuits'20046,551,870'Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer'20036,503,765'Testing vias and contacts in integrated circuit fabrication'20036,482,573'Exposure correction based on reflective index for photolithographic process control'20026,479,350'Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers'20026,368,762'Active mask exposure compensation of underlying nitride thickness variation to reduce critical dimension (CD) variation'20026,306,702'Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length'20016,287,904'Two step mask process to eliminate gate end cap shortening'20016,265,253'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'20016,221,706'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'20016,218,224'Nitride disposable spacer to reduce mask count in CMOS transistor formation'20016,214,655'Amorphous silicon disposable spacer to reduce mask count in CMOS transistor formation'20016,166,558'Method for measuring gate length and drain/source gate overlap'20006,153,455'Method of fabricating ultra shallow junction CMOS transistors with nitride disposable spacer'20006,103,563'Nitride disposable spacer to reduce mask count in CMOS transistor formation'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2003Patents assigned to ADVANCED MICRO DEVICES INC (13)· patent assignee history
2000–2019Based in San Jose, CA, US· patent location history
2000–2003Based in Sunnyvale, CA, US· patent location history
2003–2019Patents assigned to XILINX INC (11)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 13 | 2000–2003 |
| XILINX INC | 11 | 2003–2019 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 21 | 2000–2019 |
| Sunnyvale, California, US | 3 | 2000–2003 |