Inventor
Xiaowei Shen
Inventor
Hopewell Junction, NY, US
Overview
Patents· 45 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing75%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use11%
H04NPictorial communication, e.g. television4%
B05BSpraying apparatus2%
B05DProcesses for applying fluent materials to surfaces, in general2%
H01LSemiconductor devices2%
H04LTransmission of digital information, e.g. telegraphic communication2%
H05KPrinted circuits2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
PatentTitleYear
10,623,822Virtual cable modem termination system redundancy202010,098,236Use of combined masking techniques and/or combined material removal techniques to protectively coat electronic devices20189,141,547'Architecture support of best-effort atomic transactions for multiprocessor systems'20159,021,482'Reordering data responses using ordered indicia in a linked list'20159,003,169'Systems and methods for indirect register access using status-checking and status-setting instructions'20158,799,581'Cache coherence monitoring and feedback'20148,789,028'Memory access monitoring'20148,671,248'Architecture support of memory access coloring'20148,190,824'Cache line replacement monitoring and profiling'20128,166,255'Reservation required transactions'20128,140,764'System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memory'20128,140,828'Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the buffer'20128,131,938'Adaptive mechanisms and methods for supplying volatile data copies in multiprocessor systems'20128,131,894'Method and system for a sharing buffer'20127,945,741'Reservation required transactions'20117,934,061'Methods and arrangements to manage on-chip memory to reduce memory latency'20117,913,048'Data subscribe-and-publish mechanisms and methods for producer-consumer pre-fetch communications'20117,913,041'Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hint'20117,904,657'Cache residence prediction'20117,895,392'Color-based cache monitoring'20117,856,535'Adaptive snoop-and-forward mechanisms for multiprocessor systems'20107,844,778'Intelligent cache replacement mechanism with varying and adaptive temporal residency requirements'20107,676,637'Location-aware cache-to-cache transfers'20107,634,642'Mechanism to save and restore cache and translation trace for fast context switch'20097,574,562'Latency-aware thread scheduling in non-uniform cache architecture systems'20097,568,073'Mechanisms and methods of cache coherence in network-based multiprocessor systems with ring-based snoop response collection'20097,516,306'Computer program instruction architecture, system and process using partial ordering for adaptive response to memory latencies'20097,478,197'Adaptive mechanisms for supplying volatile data copies in multiprocessor systems'20097,467,280'Method for reconfiguring cache memory based on at least analysis of heat generated during runtime, at least by associating an access bit with a cache line and associating a granularity bit with a cache line in level-2 cache'20087,457,922'Cache line placement prediction for multiprocessor non-uniform cache architecture systems'20087,457,926'Cache line replacement monitoring and profiling'20087,454,573'Cost-conscious pre-emptive cache line displacement and relocation mechanisms'20087,437,517'Methods and arrangements to manage on-chip memory to reduce memory latency'20087,437,520'Adaptive snoop-and-forward mechanisms for multiprocessor systems'20087,395,407'Mechanisms and methods for using data access patterns'20087,392,352'Computer architecture for shared memory access'20087,350,034'Architecture support of best-effort atomic transactions for multiprocessor systems'20087,343,454'Methods to maintain triangle ordering of coherence messages'20087,308,538'Scope-based cache coherence'20077,287,122'Data replication in multiprocessor NUCA systems to reduce horizontal cache thrashing'20077,266,642'Cache residence prediction'20077,228,388'Enabling and disabling cache bypass using predicted cache line usage'20076,757,787'Adaptive cache coherence protocols'20046,636,950'Computer architecture for shared memory access'20036,526,481'Adaptive cache coherence protocols'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2008Patents assigned to MASSACHUSETTS INST TECHNOLOGY (4)· patent assignee history
2003–2008Based in Cambridge, MA, US· patent location history
2007–2015Patents assigned to IBM (39)· patent assignee history
2007–2015Based in Hopewell Junction, NY, US· patent location history
2012–2015Patents assigned to SHEN XIAOWEI (12)· patent assignee history
2012–2014Patents assigned to WISNIEWSKI ROBERT W (3)· patent assignee history
2012Based in Beijing, CN· patent location history
2014–2015Patents assigned to BACON DAVID F (2)· patent assignee history
2018Based in Draper, UT, US· patent location history
2020Based in Shanghai, CN· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 39 | 2007–2015 |
| SHEN XIAOWEIself | 12 | 2012–2015 |
| MASSACHUSETTS INST TECHNOLOGY | 4 | 2003–2008 |
| WISNIEWSKI ROBERT W | 3 | 2012–2014 |
| BACON DAVID F | 2 | 2014–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hopewell Junction, New York, US | 37 | 2007–2015 |
| Cambridge, Massachusetts, US | 4 | 2003–2008 |
| Beijing, CN | 2 | 2012 |
| Shanghai, CN | 1 | 2020 |
| Draper, UT, US | 1 | 2018 |