Inventor
Da Yang
Inventor
San Diego, CA, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices30%
H01LSemiconductor devices28%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
G06FElectric digital data processing4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices3%
H10BElectronic memory devices1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
10,763,364Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods202010,700,204Circuits having a diffusion break with avoided or reduced adjacent semiconductor channel strain relaxation, and related methods202010,559,501Self-aligned quadruple patterning process for Fin pitch below 20nm202010,497,702Metal-oxide semiconductor (MOS) standard cells employing electrically coupled source regions and supply rails to relax source-drain tip-to-tip spacing between adjacent MOS standard cells201910,181,403Layout effect mitigation in FinFET201910,090,244Standard cell circuits employing high aspect ratio voltage rails for reduced resistance201810,079,293Semiconductor device having a gap defined therein201810,043,796Vertically stacked nanowire field effect transistors201810,032,678Nanowire channel structures of continuously stacked nanowires for complementary metal oxide semiconductor (CMOS) devices20189,997,360Method for mitigating layout effect in FINFET20189,985,014Minimum track standard cell circuits for reduced area20189,953,979Contact wrap around structure20189,871,121'Semiconductor device having a gap defined therein'20189,859,210'Integrated circuits having reduced dimensions between components'20189,799,560'Self-aligned structure'20179,653,399'Middle-of-line integration methods and semiconductor devices'20179,620,454'Middle-of-line (MOL) manufactured integrated circuits (ICs) employing local interconnects of metal lines using an elongated via, and related methods'20179,502,283'Electron-beam (E-beam) based semiconductor device features'20169,397,007'Method for manufacturing semiconductor structure through forming an additional layer inside opening of a photoresist layer'20169,263,279'Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features'20169,245,971'Semiconductor device having high mobility channel'20168,669,160'Method for manufacturing a semiconductor device'20148,420,492'MOS transistor and method for forming the same'20137,989,804'Test pattern structure'2011Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2011Based in Singapore, SG· patent location history
2013–2016Patents assigned to INST OF MICROELECTRONICS CAS (2)· patent assignee history
2013–2014Patents assigned to YANG DA (2)· patent assignee history
2013Patents assigned to LIANG QINGQING (1)· patent assignee history
2013–2016Based in Beijing, CN· patent location history
2014Patents assigned to INST OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCE (1)· patent assignee history
2016–2020Patents assigned to QUALCOMM INC (20)· patent assignee history
2016–2020Based in San Diego, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| QUALCOMM INC | 20 | 2016–2020 |
| INST OF MICROELECTRONICS CAS | 2 | 2013–2016 |
| YANG DAself | 2 | 2013–2014 |
| INST OF MICROELECTRONICS CHINESE ACADEMY OF SCIENCE | 1 | 2014 |
| LIANG QINGQING | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Diego, California, US | 20 | 2016–2020 |
| Beijing, CN | 3 | 2013–2016 |
| Singapore, SG | 1 | 2011 |